EP3C25F324I7 Altera, EP3C25F324I7 Datasheet - Page 91

• Manufacturer Part Number: EP3C25F324I7
• Description: IC CYCLONE III FPGA 25K 324 FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C25F324I7

• Number Of Logic Elements/cells: 24624
• Number Of Labs/clbs: 1539
• Total Ram Bits: 608256
• Number Of I /o: 215
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 324-FBGA
• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 24624
• # I/os (max): 215
• Frequency (max): 437.5MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 24624
• Ram Bits: 608256
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Package Type: FBGA
• For Use With: 544-2370 - KIT STARTER CYCLONE III EP3C25
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family
PLL Reconfiguration
© December 2009
Altera Corporation
Post-Scale Counters (C0 to C4)
You can configure multiply or divide values and duty cycle of post-scale counters in
real time. Each counter has an 8-bit high time setting and an 8-bit low time setting.
The duty cycle is the ratio of output high or low time to the total cycle time, which is
the sum of the two. Additionally, these counters have two control bits, rbypass, for
bypassing the counter, and rselodd, to select the output clock duty cycle.
When the rbypass bit is set to 1, it bypasses the counter, resulting in a divide by one.
When this bit is set to 0, the PLL computes the effective division of the VCO output
frequency based on the high and low time counters. For example, if the post-scale
divide factor is 10, the high and low count values is set to 5 and 5 respectively, to
achieve a 50–50% duty cycle. The PLL implements this duty cycle by transitioning the
output clock from high-to-low on the rising edge of the VCO output clock. However,
a 4 and 6 setting for the high and low count values, respectively, would produce an
output clock with 40–60% duty cycle.
The rselodd bit indicates an odd divide factor for the VCO output frequency with a
50% duty cycle. For example, if the post-scale divide factor is three, the high and low
time count values are 2 and 1, respectively, to achieve this division. This implies a
67%–33% duty cycle. If you need a 50%–50% duty cycle, you must set the rselodd
control bit to 1 to achieve this duty cycle despite an odd division factor. The PLL
implements this duty cycle by transitioning the output clock from high-to-low on a
falling edge of the VCO output clock. When you set rselodd = 1, subtract 0.5 cycles
from the high time and add 0.5 cycles to the low time.
For example:
■
■
■
Scan Chain Description
Cyclone III device family PLLs have a 144-bit scan chain.
Table 5–4
Table 5–4. Cyclone III Device Family PLL Reprogramming Bits (Part 1 of 2)
C4
C3
C2
C1
C0
M
High time count = 2 cycles
Low time count = 1 cycle
rselodd = 1 effectively equals:
■
■
■
(1)
Block Name
High time count = 1.5 cycles
Low time count = 1.5 cycles
Duty cycle = (1.5/3)% high time count and (1.5/3)% low time count
lists the number of bits for each component of the PLL.
Counter
16
16
16
16
16
16
Number of Bits
Other
2
2
2
2
2
2
(2)
(2)
(2)
(2)
(2)
(2)
Cyclone III Device Handbook, Volume 1
Total
18
18
18
18
18
18
5–27