EP3C25F324I7 Altera, EP3C25F324I7 Datasheet - Page 191

• Manufacturer Part Number: EP3C25F324I7
• Description: IC CYCLONE III FPGA 25K 324 FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C25F324I7

• Number Of Logic Elements/cells: 24624
• Number Of Labs/clbs: 1539
• Total Ram Bits: 608256
• Number Of I /o: 215
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 324-FBGA
• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 24624
• # I/os (max): 215
• Frequency (max): 437.5MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 24624
• Ram Bits: 608256
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Package Type: FBGA
• For Use With: 544-2370 - KIT STARTER CYCLONE III EP3C25
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
Configuration Features
Figure 9–11. AP Configuration with Multiple Bus Masters
Notes to
(1) Connect the pull-up resistors to the V
(2) The nCEO pin is left unconnected or used as a user I/O pin when it does not feed the nCE pin of another device.
(3) The MSEL pin settings vary for different configuration voltage standards and POR time. To connect MSEL[3..0], refer to
(4) The AP configuration ignores the WAIT signal during configuration mode. However, if you are accessing flash during user mode with user logic,
(5) When cascading Cyclone III devices in a multi-device AP configuration, connect the repeater buffers between the master device and slave devices
(6) The other master device must fit the maximum overshoot equation outlined in
(7) The other master device can pulse nCONFIG if it is under system control rather than tied to V
© December 2009
page
you can optionally use the normal I/O to monitor the WAIT signal from the Numonyx P30 or P33 flash.
for DATA[15..0] and DCLK. All I/O inputs must maintain a maximum AC voltage of 4.1 V. The output resistance of the repeater buffers must
fit the maximum overshoot equation outlined in
Figure
9–11. Connect the MSEL pins directly to V
9–11:
Altera Corporation
Numonyx P30/P33 Flash
Figure 9–11
DQ[15:0]
A[24:1]
CCIO
RST#
ADV#
WAIT
WE#
OE#
CLK
CE#
shows the AP configuration with multiple bus masters.
supply of the bank in which the pin resides.
CCA
“Configuration and JTAG Pin I/O Requirements” on page
or GND.
Other Master Device
(6)
10 k
“Configuration and JTAG Pin I/O Requirements” on page
GND
10 k
V CCIO (1)
Cyclone III Master Device
nCE
DCLK (5)
nRESET
FLASH_nCE
nOE
nAVD
nWE
I/O (4)
DATA[15..0] (5)
PADD[23..0]
CCIO
10 k
V CCIO (1)
.
Cyclone III Device Handbook, Volume 1
9–7.
MSEL[3..0]
10 k
V CCIO (1)
nCEO
(2)
(3)
Table 9–7 on
9–7.
9–31