EP3C25F324I7 Altera, EP3C25F324I7 Datasheet - Page 60

• Manufacturer Part Number: EP3C25F324I7
• Description: IC CYCLONE III FPGA 25K 324 FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C25F324I7

• Number Of Logic Elements/cells: 24624
• Number Of Labs/clbs: 1539
• Total Ram Bits: 608256
• Number Of I /o: 215
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 324-FBGA
• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 24624
• # I/os (max): 215
• Frequency (max): 437.5MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 24624
• Ram Bits: 608256
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Package Type: FBGA
• For Use With: 544-2370 - KIT STARTER CYCLONE III EP3C25
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

4–4
Input Registers
Multiplier Stage
Cyclone III Device Handbook, Volume 1
You can send each multiplier input signal into an input register or directly into the
multiplier in 9- or 18-bit sections, depending on the operational mode of the
multiplier. Each multiplier input signal can be sent through a register independently
of other input signals. For example, you can send the multiplier Data A signal
through a register and send the Data B signal directly to the multiplier.
The following control signals are available to each input register in the embedded
multiplier:
■
■
■
All input and output registers in a single embedded multiplier are fed by the same
clock, clock enable, and asynchronous clear signals.
The multiplier stage of an embedded multiplier block supports 9 × 9 or 18 × 18
multipliers as well as other multipliers in between these configurations. Depending
on the data width or operational mode of the multiplier, a single embedded multiplier
can perform one or two multiplications in parallel. For multiplier information, refer to
“Operational Modes” on page
Each multiplier operand is a unique signed or unsigned number. Two signals, signa
and signb, control an input of a multiplier and determine if the value is signed or
unsigned. If the signa signal is high, the Data A operand is a signed number. If the
signa signal is low, the Data A operand is an unsigned number.
Table 4–3
representations. The results of the multiplication are signed if any one of the operands
is a signed value.
Table 4–3. Multiplier Sign Representation
Each embedded multiplier block has only one signa and one signb signal to control
the sign representation of the input data to the block. If the embedded multiplier
block has two 9 × 9 multipliers, the Data A input of both multipliers share the same
signa signal, and the Data B input of both multipliers share the same signb signal.
You can dynamically change the signa and signb signals to modify the sign
representation of the input operands at run time. You can send the signa and signb
signals through a dedicated input register. The multiplier offers full precision,
regardless of the sign representation.
signa Value
clock
clock enable
asynchronous clear
Unsigned
Unsigned
Signed
Signed
lists the sign of the multiplication results for the various operand sign
Data A
Logic Level
High
High
Low
Low
4–5.
Chapter 4: Embedded Multipliers in the Cyclone III Device Family
signb Value
Unsigned
Unsigned
Signed
Signed
Data B
Logic Level
© December 2009 Altera Corporation
High
High
Low
Low
Unsigned
Signed
Signed
Signed
Result
Architecture