EP3C25F324I7 Altera, EP3C25F324I7 Datasheet - Page 184

• Manufacturer Part Number: EP3C25F324I7
• Description: IC CYCLONE III FPGA 25K 324 FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C25F324I7

• Number Of Logic Elements/cells: 24624
• Number Of Labs/clbs: 1539
• Total Ram Bits: 608256
• Number Of I /o: 215
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 324-FBGA
• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 24624
• # I/os (max): 215
• Frequency (max): 437.5MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 24624
• Ram Bits: 608256
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Package Type: FBGA
• For Use With: 544-2370 - KIT STARTER CYCLONE III EP3C25
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

9–24
Cyclone III Device Handbook, Volume 1
1
1
During device configuration, Cyclone III devices read configuration data using the
parallel interface and configure their SRAM cells. This scheme is referred to as the AP
configuration scheme because the device controls the configuration interface. This
scheme contrasts with the FPP configuration scheme, where an external host controls
the interface.
AP Configuration Supported Flash Memory
The AP configuration controller in Cyclone III devices is designed to interface with
the Numonyx StrataFlash
StrataFlash Embedded Memory P33 flash family, which are two industry standard
flash families. Unlike serial configuration devices, both of the flash families supported
in the AP configuration scheme are designed to interface with microprocessors. By
configuring from an industry standard microprocessor flash which allows access to
the flash after entering user mode, the AP configuration scheme allows you to
combine configuration data and user data (microprocessor boot code) on the same
flash memory.
The Numonyx P30 and P33 flash families support a continuous synchronous burst
read mode at 40 MHz DCLK frequency for reading data from the flash. Additionally,
the Numonyx P30 and P33 flash families have identical pin-out and adopt similar
protocols for data access.
Cyclone III devices use a 40-MHz oscillator for the AP configuration scheme.
Table 9–11
configuration scheme.
Table 9–11. Supported Commodity Flash for the AP Configuration Scheme for Cyclone III
Devices
The AP configuration scheme of Cyclone III devices supports the Numonyx P30 and
P33 family 64-, 128-, and 256-Mbit flash memories. Configuring Cyclone III devices
from the Numonyx P30 and P33 family 512-Mbit flash memory is possible, but you
must properly drive the extra address and nCS pins as required by these flash
memories.
You must refer to the respective flash data sheets to check for supported speed grades
and package options.
Notes to
(1) The AP configuration scheme only supports flash memory speed grades of 40 MHz and above.
(2) 3.3- , 3.0-, 2.5-, and 1.8-V I/O options are supported for the Numonyx P30 flash family.
(3) 3.3-, 3.0- and 2.5-V I/O options are supported for the Numonyx P33 flash family.
Flash Memory Density
Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
Table
(Note 1)
128 Mbit
256 Mbit
lists the supported families of the commodity parallel flash for the AP
64 Mbit
9–11:
®
Embedded Memory P30 flash family and the Numonyx
Numonyx P30 Flash Family
v
v
v
(2)
© December 2009 Altera Corporation
Numonyx P33 Flash Family
Configuration Features
v
v
v
(3)