EP3C25F324I7 Altera, EP3C25F324I7 Datasheet - Page 117

• Manufacturer Part Number: EP3C25F324I7
• Description: IC CYCLONE III FPGA 25K 324 FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C25F324I7

• Number Of Logic Elements/cells: 24624
• Number Of Labs/clbs: 1539
• Total Ram Bits: 608256
• Number Of I /o: 215
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 324-FBGA
• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 24624
• # I/os (max): 215
• Frequency (max): 437.5MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 24624
• Ram Bits: 608256
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Package Type: FBGA
• For Use With: 544-2370 - KIT STARTER CYCLONE III EP3C25
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Chapter 6: I/O Features in the Cyclone III Device Family
I/O Banks
Table 6–5. Cyclone III Device Family I/O Standards Support
© December 2009
3.3-V LVTTL/LVCMOS,
3.0-V LVTTL/LVCMOS,
2.5-V LVTTL/LVCMOS,
1.8-V LVTTL/LVCMOS,
1.5-V LVCMOS,
1.2V LVCMOS,
3.0-V PCI / PCI-X
SSTL-18 Class I/II,
SSTL-2 Class I/II,
HSTL-18 Class I/II,
HSTL-15 Class I/II,
HSTL-12 Class I
HSTL-12 Class II
Differential SSTL-2,
Differential SSTL-18,
Differential HSTL-18,
Differential HSTL-15,
Differential HSTL-12
PPDS (2),
LVDS
BLVDS
RSDS and mini-LVDS
Differential LVPECL
Notes to
(1) These differential I/O standards are supported only for clock inputs and dedicated PLL_OUT outputs.
(2) True differential (PPDS, LVDS, mini-LVDS, and RSDS I/O standards) outputs are supported in row I/O banks only. Differential outputs in
(3) This I/O standard is supported for outputs only.
(4) This I/O standard is supported for clock inputs only.
column I/O banks require an external resistors network.
(2)
Table
(3)
6–5:
I/O Standard
Altera Corporation
(2)
Table 6–5
the I/O banks of the Cyclone III device family.
Each I/O bank of the Cyclone III device family has a VREF bus to accommodate
voltage-referenced I/O standards. Each VREF pin is the reference source for its V
group. If you use a V
VREF pin for that group to the appropriate voltage level. If you do not use all the V
groups in the I/O bank for voltage referenced I/O standards, you can use the VREF
pin in the unused voltage referenced groups as regular I/O pins. For example, if you
have SSTL-2 Class I input pins in I/O bank 1 and they are all placed in the VREFB1N0
group, VREFB1N0 must be powered with 1.25 V, and the remaining VREFB1N[1:3]
pins (if available) are used as I/O pins. If multiple V
I/O bank, the VREF pins must all be powered by the same voltage level because the
VREF pins are shorted together within the same I/O bank.
lists the I/O standards supported when a pin is used as a regular I/O pin in
(1)
(3)
(3)
(4)
v
v
v
v
—
1
REF
group for voltage-referenced I/O standards, connect the
v
v
(1)
(3)
v
v
(3)
(4)
—
2
(1)
(3)
(3)
(4)
v
v
v
v
v
3
(1)
(3)
(3)
(4)
v
v
v
v
v
4
I/O Banks
REF
(1)
(3)
(3)
(4)
v
v
v
v
—
5
groups are used in the same
Cyclone III Device Handbook, Volume 1
(1)
(3)
(3)
(4)
v
v
—
v
v
6
(1)
(3)
(3)
(4)
v
v
v
v
v
7
(1)
(3)
(3)
(4)
v
v
v
v
v
8
REF
6–17
REF