EP3C25F324I7 Altera, EP3C25F324I7 Datasheet - Page 231

• Manufacturer Part Number: EP3C25F324I7
• Description: IC CYCLONE III FPGA 25K 324 FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C25F324I7

• Number Of Logic Elements/cells: 24624
• Number Of Labs/clbs: 1539
• Total Ram Bits: 608256
• Number Of I /o: 215
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 324-FBGA
• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 24624
• # I/os (max): 215
• Frequency (max): 437.5MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 24624
• Ram Bits: 608256
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Package Type: FBGA
• For Use With: 544-2370 - KIT STARTER CYCLONE III EP3C25
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
Configuration Features
Table 9–22. Dedicated Configuration Pins on Cyclone III Device Family (Part 4 of 4)
© December 2009
DATA[7..2]
DATA[15..8]
PADD[23..0]
nRESET
nAVD
nOE
nWE
Note to
(1) AP configuration scheme is for Cyclone III devices only.
Pin Name
Table
9–22:
Altera Corporation
Mode
User
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Configuration
FPP, AP
Scheme
AP
AP
AP
AP
AP
AP
(1)
(1)
(1)
(1)
(1)
(1)
(1)
Bidirectional
Bidirectional
Pin Type
(AP)
Output
Output
Output
Output
Output
Inputs
(FPP).
(1)
Data inputs.
In AS or PS configuration schemes, they function as user I/O
pins during configuration, which means they are tri-stated.
After FPP configuration, DATA[7..2] are available as user
I/O pins and the state of these pin depends on the
Dual-Purpose Pin settings.
The byte-wide or word-wide configuration data is presented
to the target Cyclone III device on
DATA[15..0] , respectively, in the AP configuration
scheme (for Cyclone III devices only). After AP configuration,
DATA[7..2] are dedicated bidirectional pins with optional
user control.
Data inputs. Word-wide configuration data is presented to the
target Cyclone III device on DATA[15..0].
In PS, FPP, or AS configuration schemes, they function as
user I/O pins during configuration, which means they are
tri-stated.
After AP configuration, DATA[15:8] are dedicated
bidirectional pins with optional user control.
24-bit address bus from the Cyclone III device to the parallel
flash in AP mode. Connects to the A[24:1] bus on the
Numonyx P30 or P33 flash.
Active-low reset output. Driving the nRESET pin low resets
the parallel flash. Connects to the RST# pin on the Numonyx
P30 or P33 flash.
Active-low address valid output. Driving the nAVD pin low
during a read or write operation indicates to the parallel flash
that valid address is present on the PADD[23..0] address
bus. Connects to the ADV# pin on the Numonyx P30 or P33
flash.
Active-low output enable to the parallel flash. Driving the
nOE pin low during a read operation enables the parallel flash
outputs (DATA[15..0]). Connects to the OE# pin on the
Numonyx P30 or P33 flash.
Active-low write enable to the parallel flash. Driving the nWE
pin low during a write operation indicates to the parallel flash
that data on the DATA[15..0] bus is valid. Connects to
the WE# pin on the Numonyx P30 or P33 flash.
(1)
Description
Cyclone III Device Handbook, Volume 1
DATA[7..0] or
9–71