EP3C25F324I7 Altera, EP3C25F324I7 Datasheet - Page 168

• Manufacturer Part Number: EP3C25F324I7
• Description: IC CYCLONE III FPGA 25K 324 FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C25F324I7

• Number Of Logic Elements/cells: 24624
• Number Of Labs/clbs: 1539
• Total Ram Bits: 608256
• Number Of I /o: 215
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 324-FBGA
• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 24624
• # I/os (max): 215
• Frequency (max): 437.5MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 24624
• Ram Bits: 608256
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Package Type: FBGA
• For Use With: 544-2370 - KIT STARTER CYCLONE III EP3C25
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

9–8
Configuration Process
Cyclone III Device Handbook, Volume 1
f
The output resistance of the repeater buffers must fit the maximum overshoot
equation shown in
Equation 9–1.
Note to
(1)
This section describes the configuration process.
For more information about the configuration cycle state machine of Altera
refer to the
Handbook.
Power Up
If the device is powered up from the power-down state, the V
must be powered up to the appropriate level for the device to exit POR.
To begin configuration, the required voltages listed in
to the appropriate voltage levels.
Table 9–4. Power-Up Voltage for Cyclone III Device Family Configuration
Reset
When nCONFIG or nSTATUS is low, the device is in reset. Upon power-up, the
Cyclone III device family goes through POR. POR delay is dependent on the MSEL
pin settings, which correspond to the configuration scheme that you selected.
Depending on the configuration scheme, either a fast or standard POR time is
available. The fast POR time is 3 ms < TPOR < 9 ms for a fast configuration time. The
standard POR time is 50 ms < TPOR < 200 ms, which has a lower power-ramp rate.
During POR, the device resets, holds nSTATUS and CONF_DONE low, and tri-states all
user I/O pins. When the device exits POR, all user I/O pins continue to tri-state. The
user I/O pins and dual-purpose I/O pins have weak pull-up resistors that are always
enabled (after POR) before and during configuration. After POR, the Cyclone III
device family releases nSTATUS, which is pulled high by an external 10-kΩ pull-up
resistor and enters configuration mode.
When nCONFIG goes high, the device exits reset and releases the open-drain
nSTATUS pin, which is then pulled high by an external 10-kΩ pull-up resistor. After
nSTATUS is released, the device is ready to receive configuration data and the
configuration stage begins.
Notes to
(1) Voltages must be powered up to the appropriate voltage levels to begin configuration.
(2) V
Z
Cyclone III LS
O
CCIO
Equation
is the transmission line impedance and R
Cyclone III
Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
Device
Table
is for banks in which the configuration and JTAG pins reside.
Configuring Altera FPGAs
9–4:
9–1:
(Note 1)
Equation
9–1:
0.8 Z O R E 1.8Z O
chapter in volume 1 of the Configuration
Voltage that must be Powered-Up
≤
E
V
is the equivalent resistance of the output buffer.
CCBAT
≤
V
CCINT
, V
CCINT
, V
CCA
, V
, V
Table 9–4
CCA
CCIO
, V
© December 2009 Altera Corporation
CCIO
(2)
CCIO
(2)
must be powered up
for all the I/O banks
(1)
Configuration Features
®
FPGAs,