EP3C25F324I7 Altera, EP3C25F324I7 Datasheet - Page 143

IC CYCLONE III FPGA 25K 324 FBGA

EP3C25F324I7

Manufacturer Part Number
EP3C25F324I7
Description
IC CYCLONE III FPGA 25K 324 FBGA
Manufacturer
Altera
Series
Cyclone® IIIr

Specifications of EP3C25F324I7

Number Of Logic Elements/cells
24624
Number Of Labs/clbs
1539
Total Ram Bits
608256
Number Of I /o
215
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
324-FBGA
Family Name
Cyclone III
Number Of Logic Blocks/elements
24624
# I/os (max)
215
Frequency (max)
437.5MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
24624
Ram Bits
608256
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
324
Package Type
FBGA
For Use With
544-2370 - KIT STARTER CYCLONE III EP3C25
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant

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Chapter 7: High-Speed Differential Interfaces in the Cyclone III Device Family
Chapter Revision History
Chapter Revision History
Table 7–6. Chapter Revision History (Part 1 of 2)
© December 2009
December 2009
July 2009
June 2009
October 2008
Date
Altera Corporation
Table 7–6
Version
3.2
3.1
3.0
1.3
lists the revision history for this chapter.
Minor changes to the text.
Made minor correction to the part number.
Updated to include Cyclone III LS information
Updated chapter part number.
Updated “Introduction” on page 7–1, “High-Speed I/O Interface” on
page 7–1, “High-Speed I/O Standards Support” on page 7–7, “LVDS I/O
Standard Support in Cyclone III Family Devices” on page 7–7, “Designing
with LVDS” on page 7–8, “BLVDS I/O Standard Support in Cyclone III Family
Devices” on page 7–8, “RSDS, Mini-LVDS, and PPDS I/O Standard Support in
Cyclone III Family Devices” on page 7–10, “LVPECL I/O Support in Cyclone III
Family Devices” on page 7–12, “Differential SSTL I/O Standard Support in
Cyclone III Family Devices” on page 7–13, and “Differential HSTL I/O
Standard Support in Cyclone III Family Devices” on page 7–14.
Updated Figure 7–1 on page 7–2, Figure 7–4 on page 7–9, and Figure 7–5 on
page 7–10.
Updated Table 7–1 on page 7–3, Table 7–2 on page 7–4, Table 7–3 on
page 7–5, and Table 7–4 on page 7–7.
Updated Table 7–2.
Updated Table 7–1.
Updated “BLVDS I/O Standard Support in Cyclone III Devices”.
Updated “Software Overview”.
Removed registered trademark symbols for RSDS and PPDS.
Removed any mention of “RSDS and PPDS are registered trademarks of
National Semiconductor” in this chapter.
Updated chapter to new template.
Changes Made
Cyclone III Device Handbook, Volume 1
7–19

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