EP3C25F324I7 Altera, EP3C25F324I7 Datasheet - Page 153

• Manufacturer Part Number: EP3C25F324I7
• Description: IC CYCLONE III FPGA 25K 324 FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C25F324I7

• Number Of Logic Elements/cells: 24624
• Number Of Labs/clbs: 1539
• Total Ram Bits: 608256
• Number Of I /o: 215
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 324-FBGA
• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 24624
• # I/os (max): 215
• Frequency (max): 437.5MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 24624
• Ram Bits: 608256
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Package Type: FBGA
• For Use With: 544-2370 - KIT STARTER CYCLONE III EP3C25
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Chapter 8: External Memory Interfaces in the Cyclone III Device Family
Cyclone III Device Family Memory Interfaces Pin Support
Figure 8–3. DQS, CQ, or CQ# Pins for Devices in the 144-Pin EQFP and 164-Pin MBGA Packages
Optional Parity, DM, and Error Correction Coding Pins
© January 2010 Altera Corporation
Figure 8–3
banks of the Cyclone III device in the 144-pin EQFP and 164-pin MBGA packages
only.
In Cyclone III device family, the ×9 mode uses the same DQ and DQS pins as the ×8
mode, and one additional DQ pin that serves as a regular I/O pin in the ×8 mode. The
×18 mode uses the same DQ and DQS pins as ×16 mode, with two additional DQ pins
that serve as regular I/O pins in the ×16 mode. Similarly, the ×36 mode uses the same
DQ and DQS pins as the ×32 mode, with four additional DQ pins that serve as regular
I/O pins in the ×32 mode. When not used as DQ or DQS pins, the memory interface
pins are available as regular I/O pins.
Cyclone III device family supports parity in ×9, ×18, and ×36 modes. One parity bit is
available per eight bits of data pins. You can use any of the DQ pins for parity in
Cyclone III device family because the parity pins are treated and configured similar to
DQ pins.
DM pins are only required when writing to DDR2 and DDR SDRAM devices.
QDR II SRAM devices use the BWS# signal to select the byte to be written into
memory. A low signal on the DM or BWS# pin indicates the write is valid. Driving the
DM or BWS# pin high causes the memory to mask the DQ signals. Each group of DQS
and DQ signals has one DM pin. Similar to the DQ output signals, the DM signals are
clocked by the -90° shifted clock.
In Cyclone III device family, the DM pins are preassigned in the device pinouts. The
Quartus II Fitter treats the DQ and DM pins in a DQS group equally for placement
purposes. The preassigned DQ and DM pins are the preferred pins to use.
DQS1L/CQ1L#
DQS0L/CQ1L
shows the location and numbering of the DQS, DQ, or CQ# pins in I/O
I/O Bank 8
I/O Bank 3
in 144-pin EQFP and
Cyclone III Devices
164-pin MBGA
I/O Bank 7
I/O Bank 4
DQS0R/CQ1R
DQS1R/CQ1R#
Cyclone III Device Handbook, Volume 1
8–9