EP3C25F324I7 Altera, EP3C25F324I7 Datasheet - Page 207

• Manufacturer Part Number: EP3C25F324I7
• Description: IC CYCLONE III FPGA 25K 324 FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C25F324I7

• Number Of Logic Elements/cells: 24624
• Number Of Labs/clbs: 1539
• Total Ram Bits: 608256
• Number Of I /o: 215
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 324-FBGA
• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 24624
• # I/os (max): 215
• Frequency (max): 437.5MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 24624
• Ram Bits: 608256
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Package Type: FBGA
• For Use With: 544-2370 - KIT STARTER CYCLONE III EP3C25
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
Configuration Features
Table 9–14. FPP Timing Parameters for Cyclone III Device Family
© December 2009
t
t
t
t
t
t
t
t
t
t
t
t
f
t
CF 2CD
CF 2ST0
CF G
STATUS
CF 2ST1
CF 2CK
ST2C K
DSU
DH
CH
CL
CLK
M AX
CD2UM
Symbol
nCONFIG low to CONF_DONE low
nCONFIG low to nSTATUS low
nCONFIG low pulse width
nSTATUS low pulse width
nCONFIG high to nSTATUS high
nCONFIG high to first rising edge on DCLK
nSTATUS high to first rising edge of DCLK
DATA setup time before rising edge on DCLK
DATA hold time after rising edge on DCLK
DCLK high time
DCLK low time
DCLK period
DCLK frequency
CONF_DONE high to user mode
Altera Corporation
FPP Configuration Timing
Figure 9–23
external host.
Figure 9–23. FPP Configuration Timing Waveform
Notes to
(1) The beginning of this waveform shows the device in user mode. In user mode, nCONFIG, nSTATUS, and
(2) After power-up, the Cyclone III device family holds nSTATUS low during POR delay.
(3) After power-up, before and during configuration, CONF_DONE is low.
(4) Do not leave DCLK floating after configuration. It must be driven high or low, whichever is more convenient.
(5) DATA[7..0] is available as user I/O pin after configuration; the state of the pin depends on the dual-purpose pin
Table 9–14
CONF_DONE are at logic-high levels. When nCONFIG is pulled low, a reconfiguration cycle begins.
settings.
CONF_DONE (3)
Figure
nSTATUS (2)
INIT_DONE
DATA[7..0]
nCONFIG
DCLK
User I/O
Parameter
lists the FPP configuration timing parameters for Cyclone III device family.
shows the timing waveform for FPP configuration when using an
9–23:
Tri-stated with internal pull-up resistor
t
t
CFG
CF2CD
(3)
t
CF2ST1
t
CF2ST0
t
CF2CK
t
ST2CK
t
Byte 0
STATUS
t
CH
t
CLK
t
DSU
t
Byte 1
CL
t
DH
Byte 2
(Note 1)
Byte 3
(Note 1)
Minimum
(Part 1 of 2)
230
500
300
3.2
3.2
7.5
—
—
45
—
—
2
5
0
(2)
Byte n-1
Byte n
Cyclone III Device Handbook, Volume 1
t
CD2UM
Maximum
(5)
230
230
100
500
500
650
—
—
—
—
—
—
—
—
User Mode
(2)
(2)
(4)
User Mode
(4)
MHz
Unit
μs
μs
μs
μs
μs
9–47
ns
ns
ns
ns
ns
ns
ns
ns