EP3C25F324I7 Altera, EP3C25F324I7 Datasheet - Page 245

• Manufacturer Part Number: EP3C25F324I7
• Description: IC CYCLONE III FPGA 25K 324 FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C25F324I7

• Number Of Logic Elements/cells: 24624
• Number Of Labs/clbs: 1539
• Total Ram Bits: 608256
• Number Of I /o: 215
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 324-FBGA
• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 24624
• # I/os (max): 215
• Frequency (max): 437.5MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 24624
• Ram Bits: 608256
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Package Type: FBGA
• For Use With: 544-2370 - KIT STARTER CYCLONE III EP3C25
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
Remote System Upgrade
Table 9–28. Remote System Upgrade Current State Logic Contents In Status Register
© December 2009
Current State Logic
Factory information
Application information
part 1
Application information
part 2
Notes to
(1) The MSEL pin setting is in the AS or AP configuration scheme.
(2) The RSU master state machine is in factory configuration.
(3) The RSU master state machine is in application configuration.
(3)
(3)
Table
9–28:
Altera Corporation
(2)
■
■
Table 9–28
remote system upgrade master state machine is in factory configuration or
application configuration accessing the factory information or application
information respectively, and the MSEL pin setting is set to AS or AP configuration
scheme. The status register bit in
The previous two application configurations are available in the previous state
registers (previous state register 1 and previous state register 2), but only for
debugging purposes.
Table 9–29
2 in the status register when the MSEL pin setting is set to the AS or AP scheme. The
status register bit in
previous state register 1 and previous state register 2 have the same bit definitions.
The previous state register 1 reflects the current application configuration and the
previous state register 2 reflects the previous application configuration.
External configuration reset (nCONFIG) assertion
User watchdog timer time out
Status Register Bit
lists the contents of the current state logic in the status register, when the
lists the contents of the previous state register 1 and previous state register
31:30
29:24
31:30
31:30
29:24
23:0
28:0
23:0
29
Table 9–29
Master State Machine
current state
Reserved bits
Boot address
Master State Machine
current state
User watchdog timer
enable bit
User watchdog timer
time-out value
Master State Machine
current state
Reserved bits
Boot address
shows the bit positions in a 31-bit register. The
Table 9–28
Definition
lists the bit positions in a 32-bit logic.
The current state of the RSU master
state machine
Padding bits that are set to all 0's
The current 24-bit boot address that was
used by the configuration scheme as the
start address to load the current
configuration.
The current state of the RSU master
state machine
The current state of the user watchdog
enable, which is active high
The current entire 29-bit watchdog time-
out value
The current state of the RSU master
state machine
Padding bits that are set to all 0’s
The current 24-bit boot address that was
used by the configuration scheme as the
start address to load the current
configuration
(Note 1)
Cyclone III Device Handbook, Volume 1
Description
9–85