EP3C25F324I7 Altera, EP3C25F324I7 Datasheet - Page 193

• Manufacturer Part Number: EP3C25F324I7
• Description: IC CYCLONE III FPGA 25K 324 FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C25F324I7

• Number Of Logic Elements/cells: 24624
• Number Of Labs/clbs: 1539
• Total Ram Bits: 608256
• Number Of I /o: 215
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 324-FBGA
• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 24624
• # I/os (max): 215
• Frequency (max): 437.5MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 24624
• Ram Bits: 608256
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Package Type: FBGA
• For Use With: 544-2370 - KIT STARTER CYCLONE III EP3C25
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
Configuration Features
© December 2009
f
1
Altera Corporation
Programming Parallel Flash Memories
Supported parallel flash memories are external non-volatile configuration devices.
They are industry standard microprocessor flash memories. For more information
about the supported families for the commodity parallel flash, refer to
page
Cyclone III devices in a single- or multiple-device chains support in-system parallel
flash programming with the JTAG interface using the flash loader megafunction. For
Cyclone III devices, the board-intelligent host or download cable uses four JTAG pins
to program the parallel flash in system, even if the host or download cable cannot
access the configuration pins of the parallel flash.
For more information about using the JTAG pins on Cyclone III devices to program
the parallel flash in-system, refer to
(PFL) with the Quartus II
In the AP configuration scheme, the default configuration boot address is 0×010000
when represented in 16-bit word addressing in the supported parallel flash memory
(Figure
0x020000 because it is represented in 8-bit byte addressing. Cyclone III devices
configure from word address 0x010000, which is equivalent to byte address 0x020000.
The Quartus II software uses byte addressing for the default configuration boot
address. You must set the start address field to 0x020000.
The default configuration boot addressing allows the system to use special parameter
blocks in the flash memory map. Parameter blocks are at the top or bottom of the
memory map. The configuration boot address in the AP configuration scheme is
shown in
0x010000 to any desired address using the APFC_BOOT_ADDR JTAG instruction. For
more information about the APFC_BOOT_ADDR JTAG instruction, refer to
Instructions” on page
9–24.
9–13). In the Quartus II software, the default configuration boot address is
Figure
9–13. You can change the default configuration default boot address
9–61.
Software.
AN 478: Using FPGA-Based Parallel Flash Loader
Cyclone III Device Handbook, Volume 1
Table 9–11 on
“JTAG
9–33