ds2156gn Maxim Integrated Products, Inc., ds2156gn Datasheet - Page 101

• Manufacturer Part Number: ds2156gn
• Description: Ds2156, Ds2156l, Ds2156ln T1/e1/j1 Single-chip Transceiver Tdm/utopia Ii Interface
• Manufacturer: Maxim Integrated Products, Inc.

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 0/Lower CAS Align/Alarm Word (LCAW). Selects the lower CAS align/alarm bits (xyxx) to be sourced
from the lower 4 bits of the TS1 register.
Bits 1 to 7/Software Signaling Insertion Enable for LCAW and Channels 16 to 22 (CH16 to CH22). These
bits determine which channels are to have signaling inserted from the transmit signaling registers.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 0 to 7/Software Signaling Insertion Enable for Channels 22 to 30 (CH23 to CH30). These bits determine
which channels are to have signaling inserted from the transmit signaling registers.
0 = do not source the lower CAS align/alarm bits from the TS1 register
1 = source the lower CAS alarm align/bits from the TS1 register
0 = do not source signaling data from the TSx registers for this channel
1 = source signaling data from the TSx registers for this channel
0 = do not source signaling data from the TSx registers for this channel
1 = source signaling data from the TSx registers for this channel
CH22
CH30
7
7
0
0
CH21
CH29
SSIE3
Software Signaling Insertion Enable 3
0Ah
SSIE4
Software Signaling Insertion Enable 4
0Bh
6
0
6
0
CH20
CH28
5
0
5
0
CH19
CH27
4
0
4
0
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CH18
CH26
3
0
3
0
CH17
CH25
2
0
2
0
CH16
CH24
1
0
1
0
LCAW
CH23
0
0
0
0