ds2156gn Maxim Integrated Products, Inc., ds2156gn Datasheet - Page 220
ds2156gn
Manufacturer Part Number
ds2156gn
Description
Ds2156, Ds2156l, Ds2156ln T1/e1/j1 Single-chip Transceiver Tdm/utopia Ii Interface
Manufacturer
Maxim Integrated Products, Inc.
Datasheet
1.DS2156GN.pdf
(265 pages)
- Current page: 220 of 265
- Download datasheet (2Mb)
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 0 to 2/Address ESI3 Data Output Select (ESI3SEL0 to ESI3SEL2). These bits select what status is to be
output when the DS2156 decodes an ESI3 address during a bus read operation.
Bit 3/Unused, must be set to 0 for proper operation
Bits 4 to 6/Address ESI4 Data-Output Select (ESI4SEL0 to ESI4SEL2). These bits select what status is to be
output when the DS2156 decodes an ESI4 address during a bus read operation.
Bit 7/Unused, must be set to 0 for proper operation
ESI3SEL2
ESI4SEL2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
—
7
0
ESI3SEL1
ESI4SEL1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
ESI4SEL2
6
0
ESIBCR2
Extended System Information Bus Control Register 2
B1h
ESI3SEL0
ESI4SEL0
ESI4SEL1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
5
0
ESI4SEL0
Status Output
Status Output
(T1 Mode)
(T1 Mode)
SIGCHG
SIGCHG
220 of 265
4
0
ESSLIP
ESSLIP
RYEL
RYEL
LDN
LDN
RBL
RBL
LUP
LUP
—
—
—
—
—
3
0
ESI3SEL2
Status Output
Status Output
2
0
(E1 Mode)
(E1 Mode)
V52LNK
SIGCHG
V52LNK
SIGCHG
ESSLIP
ESSLIP
RDMA
RDMA
RUA1
RUA1
RRA
RRA
—
—
—
—
ESI3SEL1
1
0
ESI3SEL0
0
0
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