ds2156gn Maxim Integrated Products, Inc., ds2156gn Datasheet - Page 229

• Manufacturer Part Number: ds2156gn
• Description: Ds2156, Ds2156l, Ds2156ln T1/e1/j1 Single-chip Transceiver Tdm/utopia Ii Interface
• Manufacturer: Maxim Integrated Products, Inc.

Table 33-A. Instruction Codes for IEEE 1149.1 Architecture
SAMPLE/PRELOAD
This is a mandatory instruction for the IEEE 1149.1 specification that supports two functions. The digital
I/Os of the device can be sampled at the boundary scan register without interfering with the normal
operation of the device by using the Capture-DR state. SAMPLE/PRELOAD also allows the device to
shift data into the boundary scan register through JTDI using the Shift-DR state.
BYPASS
When the BYPASS instruction is latched into the parallel instruction register, JTDI connects to JTDO
through the 1-bit bypass test register. This allows data to pass from JTDI to JTDO without affecting the
device’s normal operation.
EXTEST
This allows testing of all interconnections to the device. When the EXTEST instruction is latched in the
instruction register, the following actions occur: Once enabled through the Update-IR state, the parallel
outputs of all digital output pins are driven. The boundary scan register is connected between JTDI and
JTDO. The Capture-DR samples all digital inputs into the boundary scan register.
CLAMP
All digital outputs of the device output data from the boundary scan parallel output while connecting the
bypass register between JTDI and JTDO. The outputs do not change during the CLAMP instruction.
HIGHZ
All digital outputs of the device are placed in a high-impedance state. The BYPASS register is connected
between JTDI and JTDO.
IDCODE
When the IDCODE instruction is latched into the parallel instruction register, the identification test
register is selected. The device identification code is loaded into the identification register on the rising
edge of JTCLK following entry into the Capture-DR state. Shift-DR can be used to shift the identification
code out serially through JTDO. During Test-Logic-Reset, the identification code is forced into the
instruction register’s parallel output. The ID code always has a 1 in the LSB position. The next 11 bits
identify the manufacturer’s JEDEC number and number of continuation bytes followed by 16 bits for the
device and 4 bits for the version (Table 33-B). Table 33-C lists the device ID codes for the SCT devices.
SAMPLE/PRELOAD
BYPASS
EXTEST
CLAMP
HIGHZ
IDCODE
INSTRUCTION
Boundary Scan
Bypass
Boundary Scan
Bypass
Bypass
Device Identification
SELECTED REGISTER
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INSTRUCTION CODES
010
111
000
011
100
001