ds2156gn Maxim Integrated Products, Inc., ds2156gn Datasheet - Page 87

• Manufacturer Part Number: ds2156gn
• Description: Ds2156, Ds2156l, Ds2156ln T1/e1/j1 Single-chip Transceiver Tdm/utopia Ii Interface
• Manufacturer: Maxim Integrated Products, Inc.

13.4 E-Bit Counter (EBCR)
This counter is only available in E1 mode. E-bit count register 1 (EBCR1) is the most significant word
and EBCR2 is the least significant word of a 16-bit counter that records far-end block errors (FEBE) as
reported in the first bit of frames 13 and 15 on E1 lines running with CRC4 multiframe. These count
registers increment once each time the received E-bit is set to 0. Since the maximum E-bit count in a one-
second period is 1000, this counter cannot saturate. The counter is disabled during loss-of-sync at either
the FAS or CRC4 level; it continues to count if loss-of-multiframe sync occurs at the CAS level.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 0 to 7/E-Bit Counter Bits 8 to 15 (EB8 to EB15). EB15 is the MSB of the 16-bit E-bit count.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 0 to 7/E-Bit Counter Bits 0 to 7 (EB0 to EB7). EB0 is the LSB of the 16-bit E-bit count.
EB15
EB7
7
7
0
0
EB14
EB6
EBCR1
E-Bit Count Register 1
48h
EBCR2
E-Bit Count Register 2
49h
6
0
6
0
EB13
EB5
5
0
5
0
EB12
EB4
4
0
4
0
87 of 265
EB11
EB3
3
0
3
0
EB10
EB2
2
0
2
0
EB9
EB1
1
0
1
0
EB8
EB0
0
0
0
0