ds2156gn Maxim Integrated Products, Inc., ds2156gn Datasheet - Page 230

• Manufacturer Part Number: ds2156gn
• Description: Ds2156, Ds2156l, Ds2156ln T1/e1/j1 Single-chip Transceiver Tdm/utopia Ii Interface
• Manufacturer: Maxim Integrated Products, Inc.

Table 33-B. ID Code Structure
Table 33-C. Device ID Codes
33.3 Test Registers
IEEE 1149.1 requires a minimum of two test registers, the boundary scan register and the bypass register.
An optional test register, the identification register, has been included with the DS2156 design. It is used
with the IDCODE instruction and the Test-Logic-Reset state of the TAP controller.
33.4 Boundary Scan Register
This register contains both a shift register path and a latched parallel output for all control cells and digital
I/O cells. It is n bits in length. See Table 33-D for cell bit locations and definitions.
33.5 Bypass Register
This is a single one-bit shift register used with the BYPASS, CLAMP, and HIGH-Z instructions that
provides a short path between JTDI and JTDO.
33.6 Identification Register
The identification register contains a 32-bit shift register and a 32-bit latched parallel output. This register
is selected during the IDCODE instruction and when the TAP controller is in the Test-Logic-Reset state.
See Table 33-B and Table 33-C for more information on bit usage.
MSB
Version
Contact Factory
4 bits
DS2156
DS2155
DS21354
DS21564
DS21352
DS21562
PART
Device ID
16 bits
16-BIT ID
0019h
0010h
0005h
0003h
0004h
0002h
JEDEC
00010100001
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LSB
1
1