ds2156gn Maxim Integrated Products, Inc., ds2156gn Datasheet - Page 170

• Manufacturer Part Number: ds2156gn
• Description: Ds2156, Ds2156l, Ds2156ln T1/e1/j1 Single-chip Transceiver Tdm/utopia Ii Interface
• Manufacturer: Maxim Integrated Products, Inc.

24.4 Fractional T1/E1 mode
In fractional T1/E1 mode, the framer is programmed to provide a gapped clock by setting CCR3.4 and
CCR3.5 = 0. The gapped clocks are synchronous with RCLK and TCLK. The UTOPIA block is
programmed to use the clock and ignore the sync signals by setting U_TCR2.1 and U_RCR2.1 = 1. In
this mode, the user can program the clock to be active during any time slot or group of time slots by using
the transmit and receive fractional channel-select function in the per-channel pointer register (PCPR). See
Section 5 for details on using this feature. In T1 mode, the F-bit is automatically gapped. In E1 mode, the
user must program the clock to be gapped during TS0 and/or TS16 if desired.
Table 24-A. UTOPIA Clock Mode Configuration
Full T1
mode, F-bit
position
gapped
Full E1
mode, TS0
and TS16
gapped
Full E1
mode, clear-
channel
(transmit)
Full E1
mode, clear-
channel
(receive)
Method #1
Full E1
mode, clear-
channel
(receive)
Method #2
Fractional T1
mode
Fractional E1
mode
MODE
U_TCFR.0
U_RCFR.0
0
1
1
1
1
0
1
CCR3.4
—
1
1
1
0
0
0
CCR3.5
—
—
1
1
1
0
0
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U_TCR2.3
X
X
X
X
X
0
1
U_TCR2.1
—
—
0
0
0
1
1
U_RCR2.1
0
0
0
1
1
1
1
Clear-channel
operation is not
available in T1
mode
Transmit framer
must be set to TS0
pass-through mode
E1TCR1.7 = 1 and
transmit-signaling
insertion disabled
Use PCPR and
PCDR1–PCDR4
registers to make
all receive channels
active
Use PCPR and
PCDR1–PCDR4
registers to select
active transmit and
receive channels
Use PCPR and
PCDR1–PCDR4
registers to select
active transmit and
receive channels
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