ds2156gn Maxim Integrated Products, Inc., ds2156gn Datasheet - Page 260

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ds2156gn

Manufacturer Part Number
ds2156gn
Description
Ds2156, Ds2156l, Ds2156ln T1/e1/j1 Single-chip Transceiver Tdm/utopia Ii Interface
Manufacturer
Maxim Integrated Products, Inc.
Datasheet
Figure 36-11. Transmit-Side Timing
Note 1: TSYNC is in the output mode (IOCR1.1 = 1).
Note 2: TSYNC is in the input mode (IOCR1.1 = 0).
Note 3: TSER is sampled on the falling edge of TCLK when the transmit-side elastic store is disabled.
Note 4: TCHCLK and TCHBLK are synchronous with TCLK when the transmit-side elastic store is disabled.
Note 5: In E1 mode, TLINK is only sampled during Sa bit locations as defined in E1TCR2; no relationship between TLCLK/TLINK and TSYNC
is implied.
TSER / TSIG /
TDATA
TCHCLK
TCHBLK
TSYNC
TSYNC
TCLK
TESO
TLCLK
TLINK
1
2
5
t
R
t D2
t
D1
t D2
t
F t
D2
t
SU
t
SU
260 of 265
t D2
t SU
t
t
HD
HD
t HD
t
CL
t
CP
t
CH

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