ds2156gn Maxim Integrated Products, Inc., ds2156gn Datasheet - Page 174

• Manufacturer Part Number: ds2156gn
• Description: Ds2156, Ds2156l, Ds2156ln T1/e1/j1 Single-chip Transceiver Tdm/utopia Ii Interface
• Manufacturer: Maxim Integrated Products, Inc.

Figure 24-4 shows an example where the ATM must pause the data transmission, since it has no data
available (in this case, for three clock cycles). This is done by deasserting UT-ENB and (optionally)
setting UT-DATAx and UT-SOC into a high-impedance state. Polling can continue. In the last clock
cycle before restarting the transmission, the address “M” of the previously selected PHY is put on the
UT-ADDRx bus to reselect PHY M again.
Figure 24-4. Transmission to PHY Paused for Three Cycles
24.5.2
The DS2156 supports direct status mode per [3] for a maximum of four PHY ports connected to one
ATM layer. For each PHY port, the status signals UR-CLAV and UT-CLAV are permanently available
according to UTOPIA Level 1 specification. PHY devices with up to four PHY ports on-chip have up to
four UR-CLAV and up to four UT-CLAV status signals, one pair of UR-CLAV and UT-CLAV for each
PHY port.
Status signals and cell transfers are independent of each other. No address information is needed to obtain
status information. Address information must be valid only for selecting a PHY port prior to one or
multiple cell transfers. With respect to the status signals UR-CLAV and UT-CLAV, this mode of
operation corresponds to that of four individual PHY devices according to UTOPIA Level 1. With respect
to the cell transfer, this mode of operation corresponds to that as described in other parts of this
document. The ATM layer selects a PHY port for cell transfer by placing the desired port on the address
lines (UR-ADDRx, UT-ADDRx), while the enable signal (UR-ENB, UT-ENB) is deasserted. All PHY
ports examine only the value on the address lines for possible selection when the enable signal is
deasserted. In case the ATM suspends transmission for a specific PHY port during a cell transfer, no cells
to/from other PHY ports can be transferred during this time.
UTOPIA Side Transmit: Direct Status Mode (Multitransmit CLAV)
CELL XMIT TO:
UT-ADDRx
UT-DATAx
UT-CLAV
UT-ENB
UT-CLK
UT-SOC
1
P31 P32 P33 P34
N
2
PHY M
N
1F
3
N+1
POLLING
4
N+1
1F
5
N-4
6
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PAUSE
SELECTION
XMIT
N-4
1F
7
M
8
P35 P36
M
1F
9
N+2
10
N+2
PHY M
P37
1F
11
POLLING
N+3
P38 P39
12
N+3
1F
13