ds2156gn Maxim Integrated Products, Inc., ds2156gn Datasheet - Page 159
ds2156gn
Manufacturer Part Number
ds2156gn
Description
Ds2156, Ds2156l, Ds2156ln T1/e1/j1 Single-chip Transceiver Tdm/utopia Ii Interface
Manufacturer
Maxim Integrated Products, Inc.
Datasheet
1.DS2156GN.pdf
(265 pages)
- Current page: 159 of 265
- Download datasheet (2Mb)
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 0/Loss of Line-Interface Transmit-Clock Condition (LOLITC). Set when TCLKI has not transitioned for
one channel time. This is a double interrupt bit (Section 6.2).
Bit 1/Transmit Open-Circuit Detect Condition (TOCD). Set when the device detects that the TTIP and TRING
outputs are open-circuited. This is a double interrupt bit (Section 6.2).
Bit 2/Transmit Current-Limit Exceeded Condition (TCLE). Set when the 50mA (RMS) current limiter is
activated, whether the current limiter is enabled or not. This is a double interrupt bit (Section 6.2).
Bit 3/Line Interface Receive Carrier-Loss Condition (LRCL). Set when the carrier signal is lost. This is a
double interrupt bit (Section 6.2).
Bit 4/Jitter Attenuator Limit Trip Event (JALT). Set when the jitter attenuator FIFO reaches to within 4 bits of
its useful limit. This bit is cleared when read. Useful for debugging jitter attenuation operation.
Bit 5/Receive Signaling Change-of-State Event (RSCOS). Set when any channel selected by the receive
signaling change-of-state interrupt-enable registers (RSCSE1 through RSCSE4) changes signaling state.
Bit 6/Timer Event (TIMER). Follows the error-counter update interval as determined by the ECUS bit in the
error-counter configuration register (ERCNT).
Bit 7/Input Level Under Threshold (ILUT). This bit is set whenever the input level at RTIP and RRING falls
below the threshold set by the value in CCR4.4 through CCR4.7. The level must remain below the programmed
threshold for approximately 50ms for this bit to be set. This is a double interrupt bit (Section 6.2).
T1: set on increments of 1 second or 42ms based on RCLK
E1: set on increments of 1 second or 62.5ms based on RCLK
ILUT
7
0
TIMER
SR1
Status Register 1
16h
6
0
RSCOS
5
0
JALT
4
0
159 of 265
LRCL
3
0
TCLE
2
0
TOCD
1
0
LOLITC
0
0
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