ds2156gn Maxim Integrated Products, Inc., ds2156gn Datasheet - Page 102

• Manufacturer Part Number: ds2156gn
• Description: Ds2156, Ds2156l, Ds2156ln T1/e1/j1 Single-chip Transceiver Tdm/utopia Ii Interface
• Manufacturer: Maxim Integrated Products, Inc.

15.2.3
In T1 mode, only registers SSIE1–SSIE3 are used since there are only 24 channels in a T1 frame.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 0 to 7/Software Signaling Insertion Enable for Channels 1 to 8 (CH1 to CH8). These bits determine which
channels are to have signaling inserted from the transmit signaling registers.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 0 to 7/Software Signaling Insertion Enable for Channels 9 to 16 (CH9 to CH16). These bits determine
which channels are to have signaling inserted from the transmit signaling registers.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 0 to 7/Software Signaling Insertion Enable for Channels 17 to 24 (CH17 to CH24). These bits determine
which channels are to have signaling inserted from the transmit signaling registers.
15.2.4
In hardware-based mode, signaling data is input through the TSIG pin. This signaling PCM stream is
buffered and inserted to the data stream being input at the TSER pin.
Signaling data can be inserted on a per-channel basis by the transmit hardware-signaling channel-select
(THSCS) function. The user has the ability to control which channels are to have signaling data from the
TSIG pin inserted into them on a per-channel basis. See Section 5 for details on using this per-channel
(THSCS) feature. The signaling insertion capabilities of the framer are available whether the transmit-
side elastic store is enabled or disabled. If the elastic store is enabled, the backplane clock (TSYSCLK)
can be either 1.544MHz or 2.048MHz. Also, if the elastic is enabled in conjunction with transmit
hardware signaling, CCR3.7 must be set = 0.
0 = do not source signaling data from the TSx registers for this channel
1 = source signaling data from the TSx registers for this channel
0 = do not source signaling data from the TSx registers for this channel
1 = source signaling data from the TSx registers for this channel
0 = do not source signaling data from the TSx registers for this channel
1 = source signaling data from the TSx registers for this channel
Software Signaling Insertion-Enable Registers, T1 Mode
Hardware-Based Mode
CH16
CH24
CH8
7
7
7
0
0
0
CH15
CH23
CH7
SSIE1
Software Signaling Insertion Enable 1
08h
SSIE2
Software Signaling-Insertion Enable 2
09h
SSIE3
Software Signaling-Insertion Enable 3
0Ah
6
0
6
0
6
0
CH14
CH22
CH6
5
0
5
0
5
0
CH13
CH21
CH5
4
0
4
0
4
0
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CH12
CH20
CH4
3
0
3
0
3
0
CH11
CH19
CH3
2
0
2
0
2
0
CH10
CH18
CH2
1
0
1
0
1
0
CH17
CH1
CH9
0
0
0
0
0
0