ds2156gn Maxim Integrated Products, Inc., ds2156gn Datasheet - Page 176

• Manufacturer Part Number: ds2156gn
• Description: Ds2156, Ds2156l, Ds2156ln T1/e1/j1 Single-chip Transceiver Tdm/utopia Ii Interface
• Manufacturer: Maxim Integrated Products, Inc.

24.5.3
The DS2156 can optionally insert a valid HEC byte in the cell header, or it can be programmed to
transparently transmit the HEC byte from ATM layer. When inserting a valid HEC byte, COSET (0x55)
addition can be optionally disabled. The generator polynomial used is 1 + X + X
idle/unassigned cell insertion (used for cell-rate decoupling), the DS2156 inserts a valid HEC byte with or
without COSET addition, depending on the TCRDS bit (U_TCR1.3). The DS2156 can optionally
scramble payload bytes, depending on the TPSE bit (U_TCR1.4) register bit. The polynomial used for
scrambling is X
HEC error in the cell header of cells transmitted in a controlled manner. If configured in HEC error-
insertion mode, it inserts HEC errors in HEC ON PERIOD number of cells and turns off HEC error
insertion for HEC OFF PERIOD number of cells set in the transmit HEC error-pattern register
(U_THEPR). This process repeats periodically, until HEC error insertion is disabled through U_TCR1.1.
Figure 24-6. Transmit Cell Flow
Transmit Processing
43
+ 1. For debugging purposes, the DS2156 can be configured to introduce a single-bit
Tx_Coset_enb
Tx_Crd_sel
HEC_OFF_period
Unassigned
Cell
HEC Insertion
ON
Cell
Idle
to Framer (PHY)
176 of 265
Scrambling
HEC Error
Cell Data
ON/OFF
Insertion
ON/OFF
Payload
HEC Insertion
Data Input
UTOPIA II
Transmit
ON/OFF
FIFO
Scrambling_enb
HEC_err_insert_enb
HEC_ON_period
HEC_insert_enb
Tx_Coset_enb
2
+ X
8
. For