ds2156gn Maxim Integrated Products, Inc., ds2156gn Datasheet - Page 151

• Manufacturer Part Number: ds2156gn
• Description: Ds2156, Ds2156l, Ds2156ln T1/e1/j1 Single-chip Transceiver Tdm/utopia Ii Interface
• Manufacturer: Maxim Integrated Products, Inc.

Normally, the clock that is output at the RCLK pin is the recovered clock from the E1 AMI/HDB3 or T1
AMI/B8ZS waveform presented at the RTIP and RRING inputs. If the jitter attenuator is placed in the
receive path (as is the case in most applications), the jitter attenuator restores the RCLK to an
approximate 50% duty cycle. If the jitter attenuator is either placed in the transmit path or is disabled, the
RCLK output can exhibit slightly shorter high cycles of the clock. This is because of the highly over-
sampled digital-clock recovery circuitry. See the Receive AC Timing Characteristics in Section 36.3 for
more details. When no signal is present at RTIP and RRING, a receive carrier loss (RCL) condition
occurs and the RCLK is derived from the JACLK source.
23.2.1
The DS2156 reports the signal strength at RTIP and RRING in 2.5dB increments through RL3–RL0
located in Information Register 2 (INFO2). This feature is helpful when trouble-shooting line-
performance problems. The DS2156 can initiate an interrupt whenever the input falls below a certain
level through the input-level under-threshold indicator (SR1.7). Using the RLT0–RLT4 bits of the CCR4
register, the user can set a threshold in 2.5dB increments. The SR1.7 bit is set whenever the input level at
RTIP and RRING falls below the threshold set by the value in RLT0–RLT4. The level must remain
below the programmed threshold for approximately 50ms for this bit to be set.
23.2.2
The DS2156 is capable of receiving a 2.048MHz square-wave synchronization clock as specified in
Section 13 of ITU G.703, October 1998. In order to use the DS2156 in this mode, set the receive
synchronization clock enable (LIC3.2) = 1.
23.2.3
Monitor applications in both E1 and T1 require various flat gain settings for the receive-side circuitry.
The DS2156 can be programmed to support these applications through the monitor mode control bits
MM1 and MM0 in the LIC3 register (Figure 23-1).
Figure 23-1. Typical Monitor Application
Receive Level Indicator and Threshold Interrupt
Receive G.703 Synchronization Signal (E1 Mode)
Monitor Mode
T1/E1 LINE
Rm
MONITOR
PORT JACK
Rm
PRIMARY
T1/E1 TERMINATING
DEVICE
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X
F
M
R
SECONDARY T1/E1
TERMINATING
DEVICE
Rt
DS2156