ds2156gn Maxim Integrated Products, Inc., ds2156gn Datasheet - Page 55

• Manufacturer Part Number: ds2156gn
• Description: Ds2156, Ds2156l, Ds2156ln T1/e1/j1 Single-chip Transceiver Tdm/utopia Ii Interface
• Manufacturer: Maxim Integrated Products, Inc.

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 0/Transmit Yellow Alarm (TYEL)
Bit 1/Transmit Blue Alarm (TBL)
Bit 2/TFDL Register Select (TFDLS)
Bit 3/Global Bit 7 Stuffing (GB7S)
Bit 4/Transmit Software Signaling Enable (TSSE).
Bit 5/Transmit CRC Pass-Through (TCPT)
Bit 6/Transmit F-Bit Pass-Through (TFPT)
Bit 7/Transmit Japanese CRC6 Enable (TJC)
0 = do not transmit yellow alarm
1 = transmit yellow alarm
0 = transmit data normally
1 = transmit an unframed all-ones code at TPOS and TNEG
0 = source FDL or Fs-bits from the internal TFDL register (legacy FDL support mode)
1 = source FDL or Fs-bits from the internal HDLC controller or the TLINK pin
0 = allow the SSIEx registers to determine which channels containing all 0s are to be bit 7 stuffed
1 = force bit 7 stuffing in all 0-byte channels regardless of how the SSIEx registers are programmed
0 = do not source signaling data from the TSx registers regardless of the SSIEx registers. The SSIEx
registers still define which channels are to have B7 stuffing
1 = source signaling data as enabled by the SSIEx registers
0 = source CRC6 bits internally
1 = CRC6 bits sampled at TSER during F-bit time
0 = F bits sourced internally
1 = F bits sampled at TSER
0 = use ANSI/AT&T/ITU CRC6 calculation (normal operation)
1 = use Japanese standard JT–G704 CRC6 calculation
TJC
7
0
TFPT
T1TCR1
T1 Transmit Control Register 1
05h
6
0
TCPT
5
0
TSSE
4
0
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GB7S
3
0
TFDLS
preformed.
2
0
TBL
1
0
TYEL
0
0