ds2156gn Maxim Integrated Products, Inc., ds2156gn Datasheet - Page 147

• Manufacturer Part Number: ds2156gn
• Description: Ds2156, Ds2156l, Ds2156ln T1/e1/j1 Single-chip Transceiver Tdm/utopia Ii Interface
• Manufacturer: Maxim Integrated Products, Inc.

22.4 Receive HDLC Code Example
The following is an example of a receive HDLC routine:
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22.5 Legacy FDL Support (T1 Mode)
22.5.1
To provide backward compatibility to the older DS21x52 T1 device, the DS2156 maintains the circuitry
that existed in the previous generation of the T1 framer. In new applications, it is recommended that the
HDLC controllers and BOC controller described in Section 20 and 22 are used.
22.5.2
In the receive section, the recovered FDL bits or Fs bits are shifted bit-by-bit into the receive FDL
register (RFDL). Because the RFDL is 8 bits in length, it fills up every 2ms (8 x 250µs). The framer
signals an external microcontroller that the buffer has filled through the SR8.3 bit. If enabled through
IMR8.3, the INT pin toggles low, indicating that the buffer has filled and needs to be read. The user has
2ms to read this data before it is lost. If the byte in the RFDL matches either of the bytes programmed
into the RFDLM1 or RFDLM2 registers, then the SR8.1 bit is set to a 1 and the INT pin toggles low if
enabled through IMR8.1. This feature allows an external microcontroller to ignore the FDL or Fs pattern
until an important event occurs.
The framer also contains a zero destuffer, which is controlled through the T1RCR2.3 bit. In both ANSI
T1.403 and TR54016, communications on the FDL follows a subset of an LAPD protocol. The LAPD
protocol states that no more than five 1s should be transmitted in a row so that the data does not resemble
an opening or closing flag (01111110) or an abort signal (11111111). If enabled through T1RCR2.3, the
DS2156 automatically looks for five 1s in a row, followed by a 0. If it finds such a pattern, it
automatically removes the zero. If the zero destuffer sees six or more 1s in a row followed by a 0, the 0 is
not removed. The T1RCR2.3 bit should always be set to a 1 when the DS2156 is extracting the FDL.
Refer to Application Note 335: DS2141A, DS2151 Controlling the FDL for information about using the
DS2156 in FDL applications in this legacy support mode.
Reset receive HDLC controller.
Set HDLC mode, mapping, and high watermark.
Start new message buffer.
Enable RPE and RHWM interrupts.
Wait for interrupt.
Disable RPE and RHWM interrupts.
Read HxRPBA register. N = HxRPBA (lower 7 bits are byte count, MSB is status).
Read (N and 7Fh) bytes from receive FIFO and store in message buffer.
Read INFO5 register.
If PS2, PS1, PS0 = 000, then go to Step 4.
If PS2, PS1, PS0 = 001, then packet terminated OK, save present message buffer.
If PS2, PS1, PS0 = 010, then packet terminated with CRC error.
If PS2, PS1, PS0 = 011, then packet aborted.
If PS2, PS1, PS0 = 100, then FIFO overflowed.
Go to Step 3.
Overview
Receive Section
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