ds2156gn Maxim Integrated Products, Inc., ds2156gn Datasheet - Page 92

• Manufacturer Part Number: ds2156gn
• Description: Ds2156, Ds2156l, Ds2156ln T1/e1/j1 Single-chip Transceiver Tdm/utopia Ii Interface
• Manufacturer: Maxim Integrated Products, Inc.

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 0/Force Receive Signaling All Ones (FRSAO). In T1 mode, this bit forces all signaling data at the RSIG and
RSER pin to all ones. This bit has no effect in E1 mode.
Bit 1/Transmit Time Slot Control for CAS Signaling (TCCS). Controls the order that signaling is transmitted
from the transmit signaling registers. This bit should be set = 0 in T1 mode.
Bit 2/Receive Time Slot Control for CAS Signaling (RCCS). Controls the order that signaling is placed into the
receive signaling registers. This bit should be set = 0 in T1 mode.
Bit 3/Receive Force Freeze (RFF). Freezes receive-side signaling at RSIG (and RSER if receive signaling
reinsertion is enabled); overrides receive freeze enable (RFE). See Section 15.1.2.3 for details.
Bit 4/Receive Freeze Enable (RFE). See Section 15.1.2.3 for details.
Bits 5, 6/Unused, must be set to 0 for proper operation
Bit 7/Global Receive Signaling Reinsertion Enable (GRSRE). This bit allows the user to reinsert all signaling
channels without programming all channels through the per-channel function.
0 = normal signaling data at RSIG and RSER
1 = force signaling data at RSIG and RSER to all ones
0 = signaling data is CAS format
1 = signaling data is CCS format
0 = signaling data is CAS format
1 = signaling data is CCS format
0 = do not force a freeze event
1 = force a freeze event
0 = no freezing of receive signaling data occurs
1 = allow freezing of receive signaling data at RSIG (and RSER if receive signaling reinsertion is enabled)
0 = do not reinsert all signaling
1 = reinsert all signaling
GRSRE
7
0
—
SIGCR
Signaling Control Register
40h
6
0
—
5
0
RFE
4
0
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RFF
3
0
RCCS
2
0
TCCS
1
0
FRSAO
0
0