ds2156gn Maxim Integrated Products, Inc., ds2156gn Datasheet - Page 3

• Manufacturer Part Number: ds2156gn
• Description: Ds2156, Ds2156l, Ds2156ln T1/e1/j1 Single-chip Transceiver Tdm/utopia Ii Interface
• Manufacturer: Maxim Integrated Products, Inc.

14.
15.
16.
17.
18.
19.
20.
21.
22.
13.3
13.4
15.1
15.2
16.1
18.1
18.2
18.3
18.4
20.1
20.2
21.1
21.2
21.3
22.1
22.2
22.3
22.4
22.5
13.2.1
13.2.2
13.3.1
13.3.2
15.1.1
15.1.2
15.2.1
15.2.2
15.2.3
15.2.4
18.1.1
18.1.2
18.2.1
18.2.2
Transmit a BOC................................................................................................................................................117
Receive a BOC.................................................................................................................................................117
22.2.1
22.3.1
22.3.2
22.3.3
22.3.4
22.3.5
22.5.1
22.5.2
22.5.3
DS0 MONITORING FUNCTION..................................................................................... 88
SIGNALING OPERATION ............................................................................................. 90
PER-CHANNEL IDLE CODE GENERATION .............................................................. 103
CHANNEL BLOCKING REGISTERS .......................................................................... 108
ELASTIC STORES OPERATION ................................................................................ 111
G.706 INTERMEDIATE CRC-4 UPDATING (E1 MODE ONLY).................................. 116
T1 BIT-ORIENTED CODE (BOC) CONTROLLER ...................................................... 117
ADDITIONAL (SA) AND INTERNATIONAL (SI) BIT OPERATION (E1 ONLY).......... 120
HDLC CONTROLLERS ............................................................................................... 133
F
E-B
R
T
I
R
T
E
M
T
R
M
M
M
B
HDLC C
HDLC M
R
L
DLE
EGACY
RAMES
RANSMIT
RANSMIT
RANSMIT
LASTIC
ASIC
ECEIVE
ECEIVE
ECEIVE
ECEIVE
INIMUM
ETHOD
ETHOD
ETHOD
T1 Operation ........................................................................................................................................85
E1 Operation ........................................................................................................................................85
T1 Operation ........................................................................................................................................86
E1 Operation ........................................................................................................................................86
Processor-Based Signaling..................................................................................................................90
Hardware-Based Receive Signaling ....................................................................................................91
Processor-Based Mode .......................................................................................................................96
Software Signaling Insertion-Enable Registers, E1 CAS Mode ........................................................100
Software Signaling Insertion-Enable Registers, T1 Mode .................................................................102
Hardware-Based Mode ......................................................................................................................102
T1 Mode .............................................................................................................................................114
E1 Mode.............................................................................................................................................114
T1 Mode .............................................................................................................................................115
E1 Mode.............................................................................................................................................115
FIFO Control ......................................................................................................................................137
Receive ..............................................................................................................................................138
Transmit .............................................................................................................................................140
FIFO Information ................................................................................................................................145
Receive Packet-Bytes Available ........................................................................................................145
HDLC FIFOs ......................................................................................................................................146
Overview ............................................................................................................................................147
Receive Section .................................................................................................................................147
Transmit Section ................................................................................................................................149
IT
-C
C
O
ODE
OUNTER
PERATION
FDL S
ONFIGURATION
O
S
APPING
1: H
2: I
3: I
S
S
BOC ......................................................................................................................... 117
HDLC C
D
TORES
UT
S
S
BOC ....................................................................................................................... 117
IGNALING
IDE
ELAY
P
IGNALING
IDE
NTERNAL
NTERNAL
-
ROGRAMMING
ARDWARE
OF
......................................................................................................................... 114
UPPORT
....................................................................................................................... 114
(EBCR) ........................................................................................................... 87
...................................................................................................................... 138
-S
M
I
ODE
NITIALIZATION
ODE
D
YNC
ETAILS
.................................................................................................................. 90
................................................................................................................ 96
R
R
E
............................................................................................................ 115
C
EGISTER
EGISTER
S
........................................................................................................... 133
(T1 M
XAMPLE
OUNT
CHEME
E
..................................................................................................... 133
XAMPLES
ODE
R
.............................................................................................. 115
.............................................................................................. 147
S
S
............................................................................................. 120
EGISTER
).......................................................................................... 147
CHEME
CHEME
..................................................................................... 104
3 of 265
B
B
(FOSCR).................................................................. 86
ASED ON
ASED ON
D
CRC4 M
OUBLE
-F
ULTIFRAME
RAME
...................................... 120
................................ 123