ds2156gn Maxim Integrated Products, Inc., ds2156gn Datasheet - Page 143

• Manufacturer Part Number: ds2156gn
• Description: Ds2156, Ds2156l, Ds2156ln T1/e1/j1 Single-chip Transceiver Tdm/utopia Ii Interface
• Manufacturer: Maxim Integrated Products, Inc.

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 0/Transmit FIFO Not Full Condition (TNF)
Bit 1/Transmit FIFO Below Low-Watermark Condition (TLWM)
Bit 2/Receive FIFO Not Empty Condition (RNE)
Bit 3/Receive FIFO Above High-Watermark Condition (RHWM)
Bit 4/Receive Packet-Start Event (RPS)
Bit 5/Receive Packet-End Event (RPE)
Bit 6/Transmit Message-End Event (TMEND)
0 = interrupt masked
1 = interrupt enabled—interrupts on rising edge only
0 = interrupt masked
1 = interrupt enabled—interrupts on rising edge only
0 = interrupt masked
1 = interrupt enabled—interrupts on rising edge only
0 = interrupt masked
1 = interrupt enabled—interrupts on rising edge only
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled
—
7
0
TMEND
IMR6, IMR7
HDLC # 1 Interrupt Mask Register 6
HDLC # 2 Interrupt Mask Register 7
21h, 23h
6
0
RPE
5
0
RPS
4
0
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RHWM
3
0
RNE
2
0
TLWM
1
0
TNF
0
0