ds2156gn Maxim Integrated Products, Inc., ds2156gn Datasheet - Page 171

• Manufacturer Part Number: ds2156gn
• Description: Ds2156, Ds2156l, Ds2156ln T1/e1/j1 Single-chip Transceiver Tdm/utopia Ii Interface
• Manufacturer: Maxim Integrated Products, Inc.

DS2156
24.5 Transmit Operation
The DS2156 interface to the ATM layer is fully compliant to the ATM Forum’s UTOPIA Level 2
specification [3]. Either direct status or multiplexed with 1CLAV mode is supported. The DS2156 can be
configured to use any address, 0 to 3, as its UTOPIA port address, and uses a 4-cell buffer for cell-rate
decoupling. The depth of the transmit FIFO is configurable to 2, 3, or 4 cells. When a port is polled and
has cell space available, the DS2156 generates a cell available signal for that port. Additionally, the
DS2156 generates a 2-cell space availability indication for each port. Note that this “2CLAV” indication
follows the timing and polling cycles of UT-CLAV.
Figure 24-2 shows the polling and cell transfer cycles for DS2156s used in a multiport configuration.
Note that UT-SOC must be aligned with the first byte transfer. The DS2156 uses UT-SOC to detect the
first byte of a cell. If a spurious UT-SOC comes during a cell transfer, then the DS2156 aligns with the
latest UT-SOC and ignores the bytes (partial cell) received thus far.
24.5.1
UTOPIA Side Transmit: Muxed Mode with One Transmit CLAV
In the following functional description, a PHY is a single DS2156 and PHYs are multiple DS2156s.
In Level 2 UTOPIA, only one PHY at a time is selected for a cell transfer. However, another PHY can be
polled for its UT-CLAV status while the selected PHY transfers data. The ATM layer polls the UT-
CLAV status of a PHY by placing its address on the transmit UTOPIA bus. The PHY drives UT-CLAV
during each cycle following one with its address on the UT-ADDRx lines. The ATM layer selects a PHY
for transfer by placing the port address of the PHY onto UT-ADDRx, when UT-ENB is deasserted during
the current clock cycle, and asserted during the next clock cycle. All PHYs only examine the value on
UT-ADDRx for selection purposes when UT-ENB is deasserted. The PHY is selected starting from the
cycle after its address is on the UT-ADDRx lines and UT-ENB is deasserted. And ending in the cycle,
another PHY is addressed for selection and UT-ENB is deasserted. Once a PHY is selected, the cell
transfer is accomplished as described by the cell-level handshake of UTOPIA Level 1. To operate a PHY
in a single PHY environment, the address pins should be set to the value programmed by the management
interface.
Figure 24-2 shows an example where PHYs are polled until the end of a cell transmission cycle. The UT-
CLAV signal shows that PHYs N - 3 and N + 3 can accept cells and PHY N + 3 is selected. The PHY is
selected with the rising clock edge #16. Immediately after the beginning of cell transmission to
PHY N + 3, the ATM layer starts polling again. Using the 2-clock polling cycles shown, up to 26 PHYs
can be polled. This maximum value can only be reached if all responses occur in minimum delays, e.g.,
as shown, where, with clock edge #15, the response of the last PHY is obtained, immediately followed by
the UT-ENB pulse to the PHYs. If an ATM implementation needs additional clock cycles to select the
PHY, fewer than 26 PHY can be polled during one cell cycle. Note that if the ATM would decide to
select PHY N again for the next cell transmission, it could leave the UT-ENB line asserted and start
transmitting the next cell with clock edge #15. This results in a back-to-back cell transmission.
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