ds2156gn Maxim Integrated Products, Inc., ds2156gn Datasheet - Page 54

• Manufacturer Part Number: ds2156gn
• Description: Ds2156, Ds2156l, Ds2156ln T1/e1/j1 Single-chip Transceiver Tdm/utopia Ii Interface
• Manufacturer: Maxim Integrated Products, Inc.

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 0/Receive-Side D4 Yellow Alarm Select (RD4YM)
Bit 1/Receive Japanese CRC6 Enable (RJC)
Bit 2/Receive-Side ZBTSI Support Enable (RZBTSI). Allows ZBTSI information to be output on RLINK pin.
Bit 3/Receive FDL Zero-Destuffer Enable (RZSE). Set this bit to 0 if using the internal HDLC/BOC controller
instead of the legacy support for the FDL. See Section 22.5 for details.
Bit 4/Receive SLC-96 Enable (RSLC96). Only set this bit to a 1 in D4/SLC-96 framing applications. See Section
22.6 for details.
Bit 5/Receive B8ZS Enable (RB8ZS)
Bit 6/Receive Frame Mode Select (RFM)
Bit 7/Unused, must be set to 0 for proper operation
0 = 0s in bit 2 of all channels
1 = a 1 in the S-bit position of frame 12 (J1 Yellow Alarm Mode)
0 = use ANSI/AT&T/ITU CRC6 calculation (normal operation)
1 = use Japanese standard JT–G704 CRC6 calculation
0 = ZBTSI disabled
1 = ZBTSI enabled
0 = zero destuffer disabled
1 = zero destuffer enabled
0 = SLC-96 disabled
1 = SLC-96 enabled
0 = B8ZS disabled
1 = B8ZS enabled
0 = D4 framing mode
1 = ESF framing mode
—
7
0
RFM
6
0
T1RCR2
T1 Receive Control Register 2
04h
RB8ZS
5
0
RSLC96
4
0
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RZSE
3
0
RZBTSI
2
0
RJC
1
0
RD4YM
0
0