ds2156gn Maxim Integrated Products, Inc., ds2156gn Datasheet - Page 123

• Manufacturer Part Number: ds2156gn
• Description: Ds2156, Ds2156l, Ds2156ln T1/e1/j1 Single-chip Transceiver Tdm/utopia Ii Interface
• Manufacturer: Maxim Integrated Products, Inc.

21.3 Method 3: Internal Register Scheme Based on CRC4 Multiframe
The receive side contains a set of eight registers (RSiAF, RSiNAF, RRA, and RSa4–RSa8) that report the
Si and Sa bits as they are received. These registers are updated with the setting of the receive CRC4
multiframe bit in Status Register 2 (SR4.1). The host can use the SR4.1 bit to know when to read these
registers. The user has 2ms to retrieve the data before it is lost. The MSB of each register is the first
received. See the following register descriptions for more details.
The transmit side also contains a set of eight registers (TSiAF, TSiNAF, TRA, and TSa4–TSa8) that,
through the transmit Sa bit control register (TSaCR), can be programmed to insert Si and Sa data. Data is
sampled from these registers with the setting of the transmit multiframe bit in Status Register 2 (SR4.4).
The host can use the SR4.4 bit to know when to update these registers. It has 2ms to update the data or
else the old data is retransmitted. The MSB of each register is the first bit transmitted. See the following
register descriptions for more details.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 0/Si Bit of Frame 0 (SiF0)
Bit 1/Si Bit of Frame 2 (SiF2)
Bit 2/Si Bit of Frame 4 (SiF4)
Bit 3/Si Bit of Frame 6 (SiF6)
Bit 4/Si Bit of Frame 8 (SiF8)
Bit 5/Si Bit of Frame 10 (SiF10)
Bit 6/Si Bit of Frame 12 (SiF12)
Bit 7/Si Bit of Frame 14 (SiF14)
SiF14
7
0
SiF12
RSiAF
Received Si Bits of the Align Frame
C8h
6
0
SiF10
5
0
SiF8
4
0
123 of 265
SiF6
3
0
SiF4
2
0
SiF2
1
0
SiF0
0
0