ds2156gn Maxim Integrated Products, Inc., ds2156gn Datasheet - Page 26

• Manufacturer Part Number: ds2156gn
• Description: Ds2156, Ds2156l, Ds2156ln T1/e1/j1 Single-chip Transceiver Tdm/utopia Ii Interface
• Manufacturer: Maxim Integrated Products, Inc.

3.2
3.2.1 Receive Side
Signal Name:
Signal Description:
Signal Type:
5-bit UTOPIA address bus driven from ATM layer to select the appropriate UTOPIA port. RX_UTOP_ADDR4 is
the MSB; RX_UTOP_ADDR0 is the LSB.
Signal Name:
Signal Description:
Signal Type:
Active-low signal asserted by the ATM layer to indicate that UR-DATAx and UR-SOC are sampled at the end of
the next cycle.
Signal Name:
Signal Description:
Signal Type:
Active-high signal asserted by the DS2156 when UR-DATAx contains the first valid byte of a cell and is enabled
only in cycles following those with UR-ENB asserted and cell transfer is in progress.
Signal Name:
Signal Description:
Signal Type:
This byte-wide data bus is driven by the DS2156 in response to the selection of one of the UTOPIA ports by the
ATM layer for cell transfer. This bus is tri-statable and is enabled only in cycles following those with UR-ENB
asserted and cell transfer is in progress for a port. UR-DATA7 is the MSB; UR-DATA0 is the LSB.
Signal Name:
Signal Description:
Signal Type:
The active-high UR-CLAV signal is asserted if a complete cell is available for transfer to the ATM layer for the
polled port. If UR-ADDRx does not match with any one of UTOPIA port addresses, this signal is tri-stated at the
chip level using the control lines detailed below. UR-CLAV0 is driven in multiplexed bus with 1CLAV polling
mode as well as direct status mode.
Signal Name:
Signal Description:
Signal Type:
Receive UTOPIA bus clock.
UTOPIA Bus
UR-ADDR0 to UR-ADDR4
Receive UTOPIA Address
Input
UR-ENB
Receive UTOPIA Enable
Input
UR-SOC
Receive UTOPIA Start of Cell
Output
UR-DATA0 to UR-DATA7
Receive UTOPIA Data Bus
Output
UR-CLAV
Receive UTOPIA Cell Available
Output
UR-CLK
Receive UTOPIA Clock
Input
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