ds2156gn Maxim Integrated Products, Inc., ds2156gn Datasheet - Page 184

• Manufacturer Part Number: ds2156gn
• Description: Ds2156, Ds2156l, Ds2156ln T1/e1/j1 Single-chip Transceiver Tdm/utopia Ii Interface
• Manufacturer: Maxim Integrated Products, Inc.

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 0 to 7/Transmit Idle/Unassigned Payload (TIUP0 to TIUP7). Holds the payload byte to be carried in octets
of idle/unassigned cells, transmitted towards line for cell rate decoupling.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 0 to 2/HEC On Period (HONP0 to HONP2). Holds the number of cells in which incorrect HEC is sent if
HEC error insertion is enabled.
Bits 3 to 7/HEC Off Period (HOFFP0 to HOFFP4). Holds the number of cells in which correct HEC is sent if
HEC error insertion is enabled.
If HEC error insertion in the transmit control register is enabled for a port, then for the HEC off period cells are
transmitted to the port with correct HEC. For the HEC on period, cells are sent with incorrect HEC. This cycle
repeats until HEC error insertion is disabled. Note that HEC error is introduced in all transmitted cells based on the
transmit HEC error-insertion pattern register, if the HEC error-insertion bit in the transmit control register is
enabled irrespective of whether the HEC insertion bit in the transmit control register is enabled or disabled.
HOFFP4
TIUP7
7
0
7
0
TIUP6
HOFFP3
U_TIUPB
UTOPIA Transmit Idle/Unassigned Payload Byte Register
54h
U_THEPR
UTOPIA Transmit HEC Error-Insertion Pattern Register
55h
6
1
6
0
TIUP5
HOFFP2
5
1
5
1
TIUP4
HOFFP1
4
0
4
0
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TIUP3
3
1
HOFFP0
3
1
TIUP2
2
0
HONP2
2
0
TIUP1
1
1
HONP1
1
0
TIUP0
0
0
HONP0
0
1