ds2156gn Maxim Integrated Products, Inc., ds2156gn Datasheet - Page 185

• Manufacturer Part Number: ds2156gn
• Description: Ds2156, Ds2156l, Ds2156ln T1/e1/j1 Single-chip Transceiver Tdm/utopia Ii Interface
• Manufacturer: Maxim Integrated Products, Inc.

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 0/Transmit HEC-Insertion Enable (THIE)
Bit 1/Transmit HEC Error-Insertion Enable (THEIE)
Bit 2/Transmit COSET-Addition Enable (TCAE)
Bit 3/Transmit Cell-Rate Decoupling Selection (TCRDS)
Bit 4/Transmit Payload-Scrambling Enable (TPSE)
Bits 5 to 7/Unassigned, must be set to 0 for proper operation
0 = HEC byte as received from ATM layer is transparently passed
1 = proper HEC value is computed and inserted in the HEC byte of the cell
0 = HEC error insertion disabled
1 = HEC errors introduced in the transmitted cells as specified by transmit HEC error-insertion pattern
register
0 = no COSET addition
1 = COSET (0x55) addition to the calculated HEC
Note that if HEC insertion is disabled, then the HEC byte is transmitted transparently (this bit does not
impact ATM layer cells). However, the HEC byte of idle/unassigned cells used for cell-rate decoupling
includes COSET addition as long as the TCAE bit is enabled.
0 = idle cell
1 = unassigned cell
0 = disabling scrambling
1 = enabling scrambling
—
7
0
—
U_TCR1
UTOPIA Transmit Control Register 1
56h
6
0
—
5
0
TPSE
4
0
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TCRDS
3
0
TCAE
2
1
THEIE
1
0
THIE
0
1