ds2156gn Maxim Integrated Products, Inc., ds2156gn Datasheet - Page 49

• Manufacturer Part Number: ds2156gn
• Description: Ds2156, Ds2156l, Ds2156ln T1/e1/j1 Single-chip Transceiver Tdm/utopia Ii Interface
• Manufacturer: Maxim Integrated Products, Inc.

6.1
The DS2156 contains an on-chip power-up reset function that automatically clears the writeable register
space immediately after power is supplied to the DS2156. The user can issue a chip reset at any time.
Issuing a reset disrupts traffic flowing through the DS2156 until the device is reprogrammed. The reset
can be issued through hardware using the TSTRST pin or through software using the SFTRST function in
the master mode register. The LIRST (LIC2.6) should be toggled from 0 to 1 to reset the line interface
circuitry. (It takes the DS2156 about 40ms to recover from the LIRST bit being toggled.) Finally, after the
TSYSCLK and RSYSCLK inputs are stable, the receive and transmit elastic stores should be reset (this
step can be skipped if the elastic stores are disabled).
6.1.1 Master Mode Register
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 0/Software-Issued Reset (SFTRST). A 0-to-1 transition causes the register space in the DS2156 to be cleared.
A reset clears all configuration and status registers. The bit automatically clears itself when the reset has completed.
Bit 1/DS2156 Operating Mode (T1/E1). Used to select the operating mode of the framer/formatter (digital)
portion of the 2156. The operating mode of the LIU must also be programmed.
Bits 2, 3/Test Mode Bits (TEST0, TEST1). Test modes are used to force the output pins of the DS2156 into
known states. This can facilitate the checkout of assemblies during the manufacturing process and also be used to
isolate devices from shared buses.
Bit 4/UTOPIA Reset (URST). A 0-to-1 transition causes the UTOPIA interface to reset.
Bits 5 to 7/Unused, must be set to 0 for proper operation
TEST1
0
0
1
1
Power-Up Sequence
0 = T1 operation
1 = E1 operation
TEST0
—
7
0
0
1
0
1
Operate normally
Force all output pins into tri-state (including all I/O pins and parallel port pins)
Force all output pins low (including all I/O pins except parallel port pins)
Force all output pins high (including all I/O pins except parallel port pins)
—
MSTRREG
Master Mode Register
00h
6
0
—
5
0
URST
4
0
Effect On Output Pins
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TEST1
3
0
TEST0
2
0
T1/E1
1
0
SFTRST
0
0