ds2156gn Maxim Integrated Products, Inc., ds2156gn Datasheet - Page 175

• Manufacturer Part Number: ds2156gn
• Description: Ds2156, Ds2156l, Ds2156ln T1/e1/j1 Single-chip Transceiver Tdm/utopia Ii Interface
• Manufacturer: Maxim Integrated Products, Inc.

Figure 24-5 shows an example of direct status for the transmit direction. Signals UT-CLAV[3:0] are
associated to PHY port addresses #4, #3, #2, and #1. There is no need for a unique null device, thus “X =
don’t care” represents any address between 0 and 31 on the address lines UT-ADDRx or any data on the
data bus. The polling of PHY ports starts while no cell transfer takes place. The ATM layer has pending
cells for all four PHY ports (one individual queue for each PHY port) but all four PHY ports cannot
accept a cell. With rising clock edge #2, PHY port #1 indicates that it can accept a complete cell
(UT-CLAV0 asserted). The ATM layer detects this at clock edge #3. It selects that PHY port by placing
address #1 on the address lines with rising clock edge #3. PHY port #1 detects this at clock edge #4. At
clock edge #5, PHY port #1 detects UT-ENB asserted, therefore cell transfer for PHY port #1 starts with
rising clock edge #5 (byte H1).
Figure 24-5. Example of Direct Status Indication, Transmit Direction
At clock edge #5, the ATM layer detects a cell available at PHY port #3 (UT-CLAV2 asserted). With
rising clock edge #52, PHY port #1 indicates that it cannot accept an additional cell by deasserting UT-
CLAV0. Thus, at clock edge #57, the ATM layer detects only UT-CLAV2 asserted (UT-CLAV1 and UT-
CLAV3 remain deasserted). The ATM layer deselects PHY port #1 and selects PHY port #3 for cell
transfer with rising clock edge #57 by placing address #3 on the address lines and deasserting UT-ENB.
PHY port #1 and PHY port #3 detect this at clock edge #58. At clock edge #59, PHY port #3 detects
UT-ENB asserted, therefore cell transfer for PHY port #3 starts with rising clock edge #59 (byte H1). For
additional examples, refer to [3].
UT-CLAV(1)
UT-CLAV(2)
UT-CLAV(3)
UT-CLAV(4)
UT-ADDRx
UT-DATAx
UT-ENB
UT-CLK
UT-SOC
PORT #1
PORT #2
PORT #3
PORT #4
1
X
2
X
3
1
4
H1
5
X
H2
6
175 of 265
N-4
52
Port #1 Transfer
P44
53
X = Don't Care
P45 P46
54
55
P47
56
P48
57
X
3
58
Port #3
H1
59
X