ds2156gn Maxim Integrated Products, Inc., ds2156gn Datasheet - Page 154

• Manufacturer Part Number: ds2156gn
• Description: Ds2156, Ds2156l, Ds2156ln T1/e1/j1 Single-chip Transceiver Tdm/utopia Ii Interface
• Manufacturer: Maxim Integrated Products, Inc.

23.7 LIU Control Registers
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 0/Transmit Power-Down (TPD)
Bit 1/Disable Jitter Attenuator (DJA)
Bit 2/Jitter Attenuator Buffer Depth Select (JABDS)
Bit 3/Jitter Attenuator Select (JAS)
Bit 4/Receive Equalizer Gain Limit (EGL). This bit controls the sensitivity of the receive equalizer.
Bits 5 to 7/Line Buildout Select (L0 to L2). When using the internal termination, the user needs only to select 000
for 75Ω operation or 001 for 120Ω operation below. This selects the proper voltage levels for 75Ω or 120Ω
operation. Using TT0 and TT1 of the LICR4 register, the user can then select the proper internal source
termination. Line buildouts 100 and 101 are for backwards compatibility with older products only.
E1 Mode
*TT0 and TT1 of LIC4 register must be set to 0 in this configuration.
L2
0
0
1
1
L1
0 = powers down the transmitter and tri-states the TTIP and TRING pins
1 = normal transmitter operation
0 = jitter attenuator enabled
1 = jitter attenuator disabled
0 = 128 bits
1 = 32 bits (use for delay-sensitive applications)
0 = place the jitter attenuator on the receive side
1 = place the jitter attenuator on the transmit side
T1 Mode
0 = -36dB (long haul)
1 = 15dB (limited long haul)
E1 Mode
0 = -10dB (short haul)
1 = -43dB (long haul)
0
0
0
0
L2
L0
7
0
0
1
0
1
75Ω normal
120Ω normal
75Ω with high return loss
120Ω with high return loss
L1
LIC1
Line Interface Control 1
78h
6
0
Application
L0
5
0
*
EGL
*
4
0
154 of 265
JAS
3
0
N (1)
1:2
1:2
1:2
1:2
JABDS
2
0
Return Loss
21dB
21dB
NM
NM
DJA
1
0
Rt (1) (Ω)
11.6
6.2
TPD
0
0
0
0