ds2156gn Maxim Integrated Products, Inc., ds2156gn Datasheet - Page 181

• Manufacturer Part Number: ds2156gn
• Description: Ds2156, Ds2156l, Ds2156ln T1/e1/j1 Single-chip Transceiver Tdm/utopia Ii Interface
• Manufacturer: Maxim Integrated Products, Inc.

An example for the receive direction is shown in Figure 24-11. The status signals UR-CLAVx are
associated to PHY port addresses #4, #3, #2, and #1. There is no need for a unique null device so “X =
don’t care” on the address lines UR-ADDRx.
In Figure 24-11, the polling of PHY ports starts while no cell transfer takes place. The ATM layer
monitors all four status signals UR-CLAVx. At clock edge #3 it detects a cell available at PHY port #1,
UR-CLAV(1) asserted. It selects that PHY port by placing address #1 on the address lines with rising
clock edge #3. PHY port #1 detects this at clock edge #4. At clock edge #5, PHY port #1 detects
UR-ENB asserted, thus cell transfer for PHY port #1 starts with rising clock edge #5.
At clock edge #5 the ATM layer detects a cell available at PHY port #3, UR-CLAV(3) asserted. Not
knowing whether PHY port #1 may have another cell available or not, the ATM layer deselects PHY port
#1 and selects PHY port #3 for cell transfer with rising clock edge #57 by placing address #3 on the
address lines and deasserting UR-ENB. PHY port #1 and PHY port #3 detect this at clock edge #58. At
clock edge #59, PHY port #3 detects UR-ENB asserted, thus cell transfer starts with rising clock edge
#59. At clock edge #111, no cell is available at PHY ports #1, #2, and #4. The ATM layer keeps
UR-ENB asserted and detects at clock edge #113 the first byte of another cell available from PHY port
#3, UR-CLAV(3) asserted. Thus, cell transfer takes place starting with rising clock edge #112. At clock
edge #164, again, no cell is available at PHY ports #1, #2, and #4. The ATM layer keeps the UR-ENB
asserted and also detects at clock edge #166 no cell available from PHY port #3, UR-CLAV(3)
deasserted. Thus, the ATM layer deselects PHY port #3 by deasserting UR-ENB with rising clock edge
#166.
Figure 24-11. Example of Direct Status Indication, Receive Direction
UR-CLAV(1)
UR-CLAV(2)
UR-CLAV(3)
UR-CLAV(4)
UR-ADDRx
UR-DATAx
UR-ENB
UR-CLK
UR-SOC
PORT #1
PORT #2
PORT #3
PORT #4
1
X
2
3
1
4
5
X
H1
Cell Transfer
6
(port #1)
57
P48
3
58
181 of 265
59
X
H1
Cell Transfer
60
(port #3)
111
P48
112
X
H1
113
Cell Transfer
(port #3)
H2
114
164
P48
165
X
166
X
167