ds2156gn Maxim Integrated Products, Inc., ds2156gn Datasheet - Page 51

• Manufacturer Part Number: ds2156gn
• Description: Ds2156, Ds2156l, Ds2156ln T1/e1/j1 Single-chip Transceiver Tdm/utopia Ii Interface
• Manufacturer: Maxim Integrated Products, Inc.

condition. For example, SR2 has a bit that is set when the device goes into a loss-of-sync state (SR2.0, a
condition bit) and a bit that is set (SR2.4, an event bit) when the loss-of-sync condition clears (goes in
sync). Some of the status register bits (condition bits) do not have a separate bit for the “condition clear”
event but rather the status bit can produce interrupts on both edges, setting and clearing. These bits are
marked as double interrupt bits. An interrupt is produced when the condition occurs and when it clears.
6.4
Information registers operate the same as status registers except they cannot cause interrupts. They are all
latched except for INFO7 and some of the bits in INFO5 and INFO6. INFO7 register is a read-only
register. It reports the status of the E1 synchronizer in real time. INFO7 and some of the bits in INFO6
and INFO5 are not latched and it is not necessary to precede a read of these bits with a write.
6.5
The interrupt information registers provide an indication of which status registers (SR1 through SR9) are
generating an interrupt. When an interrupt occurs, the host can read IIR1 and IIR2 to quickly identify
which of the nine status registers are causing the interrupt.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Information Registers
Interrupt Information Registers
SR8
—
7
7
0
0
SR7
—
IIR1
Interrupt Information Register 1
14h
IIR2
Interrupt Information Register 2
15h
6
0
6
0
SR6
—
5
0
5
0
SR5
—
4
0
4
0
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SR4
—
3
0
3
0
SR3
—
2
0
2
0
U_RSR
SR2
1
0
1
0
SR1
SR9
0
0
0
0