ds2156gn Maxim Integrated Products, Inc., ds2156gn Datasheet - Page 52

• Manufacturer Part Number: ds2156gn
• Description: Ds2156, Ds2156l, Ds2156ln T1/e1/j1 Single-chip Transceiver Tdm/utopia Ii Interface
• Manufacturer: Maxim Integrated Products, Inc.

7. CLOCK MAP
Figure 7-1 shows the clock map of the DS2156. The routing for the transmit and receive clocks are shown
for the various loopback modes and jitter attenuator positions. Although there is only one jitter attenuator,
which can be placed in the receive or transmit path, two are shown for simplification and clarity.
Figure 7-1. Clock Map (TDM Mode)
The TCLK MUX is dependent on the state of the TCSS0 and TCSS1 bits in the LIC1 register and the
state of the TCLK pin.
TCSS1
RXCLK
TXCLK
TO
LIU
0
0
1
1
MCLKS = 0
RCL = 1
RCL = 0
TCSS0
2.048 TO 1.544
SYNTHESIZER
PRE-SCALER
MCLK
0
1
0
1
LOCAL
LOOPBACK
LLB = 0
LLB = 1
MCLKS = 1
The TCLK pin (C) is always the source of transmit clock.
Switch to the recovered clock (B) when the signal at the TCLK pin
fails to transition after one channel time.
Use the scaled signal (A) derived from MCLK as the transmit clock.
The TCLK pin is ignored.
Use the recovered clock (B) as the transmit clock. The TCLK pin is
ignored.
LIC4.MPS0
LIC4.MPS1
LIC2.3
JITTER ATTENUATOR
SEE LIC1 REGISTER
JAS = 0
OR
DJA = 1
JAS = 1
AND
DJA = 0
LTCA
LTCA
JAS = 0
AND
DJA = 0
JAS = 1
OR
DJA = 1
REMOTE
LOOPBACK
Transmit Clock Source
RLB = 1
RLB = 0
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DJA = 1
DJA = 0
FRAMER
LOOPBACK
FLB = 0
FLB = 1
TRANSMIT
FORMATTER
RECEIVE
FRAMER
8 x PLL
PAYLOAD
LOOPBACK
(SEE NOTES)
PLB = 1
PLB = 0
A
B
BPCLK
SYNTH
C
TCLK
MUX
TSYSCLK
8XCLK
BPCLK
RCLK
TCLK