ds2156gn Maxim Integrated Products, Inc., ds2156gn Datasheet - Page 8

• Manufacturer Part Number: ds2156gn
• Description: Ds2156, Ds2156l, Ds2156ln T1/e1/j1 Single-chip Transceiver Tdm/utopia Ii Interface
• Manufacturer: Maxim Integrated Products, Inc.

DS2156
LIST OF TABLES
Table 3-A. Pin Description Sorted by Pin Number (TDM Backplane Enabled) ........................................ 34
Table 3-B. Pin Description Sorted by Pin Number (UTOPIA Backplane Enabled)................................... 36
Table 4-A. Register Map Sorted by Address ............................................................................................ 39
Table 4-B. UTOPIA Register Map ............................................................................................................ 45
Table 8-A. T1 Alarm Criteria..................................................................................................................... 61
Table 9-A. E1 Sync/Resync Criteria ......................................................................................................... 63
Table 9-B. E1 Alarm Criteria..................................................................................................................... 68
Table 13-A. T1 Line Code Violation Counting Options ............................................................................. 83
Table 13-B. E1 Line-Code Violation Counting Options ............................................................................83
Table 13-C. T1 Path Code Violation Counting Arrangements .................................................................. 85
Table 13-D. T1 Frames Out-of-Sync Counting Arrangements ................................................................. 86
Table 15-A. Time Slot Numbering Schemes ............................................................................................ 97
Table 16-A. Idle-Code Array Address Mapping...................................................................................... 103
Table 16-B. GRIC and GTIC Functions .................................................................................................. 105
Table 18-A. Elastic Store Delay After Initialization ................................................................................. 115
Table 22-A. HDLC Controller Registers ................................................................................................. 134
Table 23-A. Transformer Specifications ................................................................................................. 163
Table 24-A. UTOPIA Clock Mode Configuration ....................................................................................170
Table 27-A. Transmit Error-Insertion Setup Sequence .......................................................................... 211
Table 27-B. Error Insertion Examples .................................................................................................... 213
Table 33-A. Instruction Codes for IEEE 1149.1 Architecture ................................................................. 229
Table 33-B. ID Code Structure ............................................................................................................... 230
Table 33-C. Device ID Codes................................................................................................................. 230
Table 33-D. Boundary Scan Control Bits................................................................................................ 231
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