ds2156gn Maxim Integrated Products, Inc., ds2156gn Datasheet - Page 240

• Manufacturer Part Number: ds2156gn
• Description: Ds2156, Ds2156l, Ds2156ln T1/e1/j1 Single-chip Transceiver Tdm/utopia Ii Interface
• Manufacturer: Maxim Integrated Products, Inc.

Figure 34-13. Receive-Side Boundary Timing, RSYSCLK = 1.544MHz (Elastic
Store Enabled)
Note 1: Data from the E1 channels 1, 5, 9, 13, 17, 21, 25, and 29 is dropped (channel 2 from the E1 link is mapped to channel 1 of the T1 link,
Note 2: RSYNC in the output mode (IOCR1.4 = 0).
Note 3: RSYNC in the input mode (IOCR1.4 = 1).
Note 4: RCHBLK is programmed to block channel 24.
Figure 34-14. Receive-Side Boundary Timing, RSYSCLK = 2.048MHz (Elastic
Store Enabled)
Note 1: RSYNC is in the output mode (IOCR1.4 = 0).
Note 2 : RSYNC is in the input mode (IOCR1.4 = 1).
Note 3: RCHBLK is programmed to block channel 1.
Note 4: RSIG normally contains the CAS multiframe alignment nibble (0000) in channel 1.
etc.) and the F-bit position is added (forced to on 1).
RCHBLK
RSYSCLK
RSYSCLK
RCHBLK
RMSYNC
RCHCLK
RMSYNC
RSYNC
RSYNC
RCHCLK
RSYNC
RSYNC
RSER
RSER
RSIG
3
1
2
4
2
1
3
CHANNEL 23/31
CHANNEL 31
A
CHANNEL 31
B
LSB
C
MSB
LSB MSB
D
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CHANNEL 24/32
CHANNEL 32
A
CHANNEL 32
B
LSB
C
F
LSB MSB
D
MSB
CHANNEL 1/2
CHANNEL 1
CHANNEL 1
Note 4