ds2156gn Maxim Integrated Products, Inc., ds2156gn Datasheet - Page 210

• Manufacturer Part Number: ds2156gn
• Description: Ds2156, Ds2156l, Ds2156ln T1/e1/j1 Single-chip Transceiver Tdm/utopia Ii Interface
• Manufacturer: Maxim Integrated Products, Inc.

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 0/BERT Enable (BERTEN)
Bit 1/BERT Direction (BERTDIR)
Bits 2, 5, 7/Unused, must be set to 0 for proper operation
Bit 3/Transmit Framed/Unframed Select (TFUS)
Bit 4/Transmit Byte-Align Toggle (TBAT). A 0-to-1 transition forces the BERT to byte align its pattern with the
transmit formatter. This bit must be transitioned in order to byte align the Daly pattern.
Bit 6/Receive Framed/Unframed Select (RFUS)
0 = BERT disabled
1 = BERT enabled
0 = network
BERT transmits toward the network (TTIP and TRING) and receives from the network (RTIP and
RRING). The BERT pattern can be looped back to the receiver internally by using the framer loopback
function.
1 = system
BERT transmits toward the system backplane (RSER) and receives from the system backplane (TSER).
0 = BERT does not source data into the F-bit position (framed)
1 = BERT does source data into the F-bit position (unframed)
0 = BERT is not sent data from the F-bit position (framed)
1 = BERT is sent data from the F-bit position (unframed)
—
7
0
RFUS
BIC
BERT Interface Control Register
EAh
6
0
—
5
0
TBAT
4
0
210 of 265
TFUS
3
0
—
2
0
BERTDIR
1
0
BERTEN
0
0