ds2156gn Maxim Integrated Products, Inc., ds2156gn Datasheet - Page 80

• Manufacturer Part Number: ds2156gn
• Description: Ds2156, Ds2156l, Ds2156ln T1/e1/j1 Single-chip Transceiver Tdm/utopia Ii Interface
• Manufacturer: Maxim Integrated Products, Inc.

12.1 Per-Channel Loopback
The per-channel loopback registers (PCLRs) determine which channels (if any) from the backplane
should be replaced with the data from the receive side or, i.e., off of the T1 or E1 line. If this loopback is
enabled, then transmit and receive clocks and frame syncs must be synchronized. One method to
accomplish this is to connect RCLK to TCLK and RFSYNC to TSYNC. There are no restrictions on
which channels can be looped back or on how many channels can be looped back.
Each of the bit positions in the per-channel loopback registers (PCLR1/PCLR2/PCLR3/PCLR4)
represents a DS0 channel in the outgoing frame. When these bits are set to a 1, data from the
corresponding receive channel replaces the data on TSER for that channel.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 0 to 7/Per-Channel Loopback Enable for Channels 1 to 8 (CH1 to CH8)
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 0 to 7/Per-Channel Loopback Enable for Channels 9 to 16 (CH9 to CH16)
0 = loopback disabled
1 = enable loopback; source data from the corresponding receive channel
0 = loopback disabled
1 = enable loopback; source data from the corresponding receive channel
CH16
CH8
7
7
0
0
CH15
CH7
PCLR1
Per-Channel Loopback Enable Register 1
4Bh
PCLR2
Per-Channel Loopback Enable Register 2
4Ch
6
0
6
0
CH14
CH6
5
0
5
0
CH13
CH5
4
0
4
0
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CH12
CH4
3
0
3
0
CH11
CH3
2
0
2
0
CH10
CH2
1
0
1
0
CH1
CH9
0
0
0
0