ds2156gn Maxim Integrated Products, Inc., ds2156gn Datasheet - Page 239

• Manufacturer Part Number: ds2156gn
• Description: Ds2156, Ds2156l, Ds2156ln T1/e1/j1 Single-chip Transceiver Tdm/utopia Ii Interface
• Manufacturer: Maxim Integrated Products, Inc.

34.2 E1 Mode
Figure 34-11. Receive-Side Timing
Note 1: RSYNC in frame mode (IOCR1.5 = 0).
Note 2: RSYNC in multiframe mode (IOCR1.5 = 1).
Note 3: RLCLK is programmed to output just the Sa bits.
Note 4: RLINK always outputs all five Sa bits as well as the rest of the receive data stream.
Note 5: This diagram assumes the CAS MF begins in the RAF frame.
Figure 34-12. Receive-Side Boundary Timing (with Elastic Store Disabled)
Note 1: RCHBLK is programmed to block channel 1.
Note 2: RLCLK is programmed to mark the Sa4 bit in RLINK.
Note 3: Shown is a RNAF frame boundary.
Note 4: RSIG normally contains the CAS multiframe alignment nibble (0000) in channel 1.
RFSYNC
RSYNC
RSYNC
RLCLK
FRAME#
RLINK
RCHBLK
RFSYNC
RCHCLK
RSYNC
RLINK
RLCLK
RSER
RCLK
RSIG
2
4
3
1
1
2
1
CHANNEL 32
CHANNEL 32
2
A
3
B
4
C
LSB
D
5
Si
6
1
7
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A Sa4 Sa5 Sa6 Sa7 Sa8
8
Sa4 Sa5 Sa6 Sa7 Sa8
CHANNEL 1
CHANNEL 1
9
Note 4
10
11
12
MSB
13
14
CHANNEL 2
CHANNEL 2
15
A
16
B
1