ds2156gn Maxim Integrated Products, Inc., ds2156gn Datasheet - Page 188

• Manufacturer Part Number: ds2156gn
• Description: Ds2156, Ds2156l, Ds2156ln T1/e1/j1 Single-chip Transceiver Tdm/utopia Ii Interface
• Manufacturer: Maxim Integrated Products, Inc.

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 0 to 7/Receive Correctable HEC Counter (RCHC0 to RCHC7)
Note that write access to the receive PMON-counter latch-enable register latches all receive PMON-counter values
into temporary latch registers and clears the internal count values. This register holds the number of correctable
HEC-errored cells received since last latching. Note that this count corresponds to cells received when cell
delineation is in SYNC. A correctable HEC-errored cell is a cell with a single-bit error, provided single-bit HEC-
error correction is enabled through U_RCR1.1 and the receiver mode of operation is in correction mode.
Correctable HEC count value is unaffected if HEC-error correction is disabled.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 0 to 3/Receive Uncorrectable HEC Counter (RUHC8 to RUHC11)
Bits 4 to 7/Unused
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 0 to 7/Receive Uncorrectable HEC Counter (RUHC0 to RUHC7)
The U_RUHEC1 and U_RUHEC2 registers count the number of uncorrectable HEC-errored cells received since
last latching. Note that this count corresponds to cells received when cell delineation is in SYNC. For every SYNC-
to-HUNT transition of the cell delineation state machine, the “Correctable + Uncorrectable” error-count value
increases by 6 instead of 7. For every SYNC-to-HUNT transition, if HEC correction is enabled, the correctable
HEC count increases by 1 and the uncorrectable HEC count increases by 5. If HEC correction is disabled,
correctable HEC count is not affected and uncorrectable HEC count increases by 6. Note that cell delineation goes
to HUNT state upon the reception of the 7th consecutive HEC pattern. Receive PMON counters are not updated
when cell delineation is out of SYNC state. Note that write access to the receive PMON-counter latch-enable
register latches internal receive PMON-counter values and clears them once they are latched.
RCHC7
RUHC7
—
7
7
7
0
0
0
RUHC6
RCHC6
—
U_RCHEC
UTOPIA Receive Correctable HEC Counter Register
63h
U_RUHEC1
UTOPIA Receive Uncorrectable HEC Counter Register 1
64h
U_RUHEC2
UTOPIA Receive Uncorrectable HEC Counter Register 2
65h
6
0
6
0
6
0
RUHC5
RCHC5
—
5
0
5
0
5
0
RCHC4
RUHC4
—
4
0
4
0
4
0
188 of 265
RUHC11
RCHC3
RUHC3
3
0
3
0
3
0
RUHC2
RCHC2
RUHC10
2
0
2
0
2
0
RCHC1
RUHC1
RUHC9
1
0
1
0
1
0
RUHC0
RCHC0
RUHC8
0
0
0
0
0
0