ds2156gn Maxim Integrated Products, Inc., ds2156gn Datasheet - Page 187

• Manufacturer Part Number: ds2156gn
• Description: Ds2156, Ds2156l, Ds2156ln T1/e1/j1 Single-chip Transceiver Tdm/utopia Ii Interface
• Manufacturer: Maxim Integrated Products, Inc.

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 0 to 7/Receive LCD Integration Period (RLIP0 to RLIP7)
This 8-bit register holds the LCD integration period value for which the out-of-cell delineation condition must
persist for declaring loss-of-cell delineation (LCD). For deasserting LCD, cell delineation should persist in the
SYNC state for the same amount of time programmed in this register. LCD state change condition can be
programmed to generate an external interrupt through U_RCR2.4. A value of 0 programmed into this register
declares LCD for every OCD condition at the resolution of the internal system clock period. The internal system
clock is 8x the line clock [16.383MHz (E1 mode) and 12.352MHz (T1 mode)].
For example, in E1 mode a register value of 64h (100) generates a 100ms integration time. In T1 mode, a register
value of 4Bh (75) generates a 100ms integration time.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 0 to 7/The host should always write 0x00 to this register when latching the receive PMON counter.
This register is provided for latching all receive PMON-counter values, namely the 16-bit receive assigned cell-
count value, 12-bit receive uncorrectable HEC-count value, and 8-bit receive correctable HEC-count value of a port
into the common receive assigned cell-counter latch register, receive uncorrectable HEC-counter latch register, and
receive correctable HEC-count latch register, respectively. A write into this register clears the receive PMON
counters for that port.
IT = Integration Time in ms
For E1 mode, register value = IT / 1ms
For T1 mode, register value = IT / 1.326ms
RLIP7
—
7
7
0
0
RLIP6
—
U_RLCDIP
UTOPIA Receive LCD Integration Period Register
61h
U_RPCE
UTOPIA Receive PMON-Counter Enable Register
62h
6
1
6
0
RLIP5
—
5
1
5
0
RLIP4
—
4
0
4
0
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RLIP3
—
3
0
3
0
RLIP2
—
2
1
2
0
RLIP1
—
1
1
1
0
RLIP0
—
0
0
0
0