ds2156gn Maxim Integrated Products, Inc., ds2156gn Datasheet - Page 189

• Manufacturer Part Number: ds2156gn
• Description: Ds2156, Ds2156l, Ds2156ln T1/e1/j1 Single-chip Transceiver Tdm/utopia Ii Interface
• Manufacturer: Maxim Integrated Products, Inc.

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits0 to 7/Receive-Assigned Cell Count 8 to 15 (RACC8 to RACC15)
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 0 to 7/Receive-Assigned Cell Count 0 to 7 (RACC0 to RACC7)
The U_RACC1 and U_RACC2 registers are common registers for all ports. For software convenience, any of the
eight addresses can be used to access these registers. For reading the 16-bit receive assigned cell count for a port,
software has to write into the receive PMON-counter latch-enable register for the port before reading from these
registers. Reading from these registers without writing into the latch-enable register returns the old value that was
latched and not the current value of the receive-assigned cell count of a port. The assigned cell count value reflects
the number of cells written into receive FIFO that can be read by the ATM layer since last latching. Note that
whether or not the ATM layer dequeues cells from the receive FIFO, the assigned cell counter of a port is
incremented upon the reception of a valid ATM layer cell when cell delineation is in SYNC state.
RACC15
RACC7
7
7
0
0
RACC14
RACC6
U_RACC1
UTOPIA Receive-Assigned Cell Count Register 1
66h
U_RACC2
UTOPIA Receive-Assigned Cell Count Register 2
67h
6
0
6
0
RACC13
RACC5
5
0
5
0
RACC4
RACC12
189 of 265
4
0
4
0
RACC11
RACC3
3
0
3
0
RACC10
RACC2
2
0
2
0
RACC9
RACC1
1
0
1
0
RACC0
RACC8
0
0
0
0