ds2156gn Maxim Integrated Products, Inc., ds2156gn Datasheet - Page 173

• Manufacturer Part Number: ds2156gn
• Description: Ds2156, Ds2156l, Ds2156ln T1/e1/j1 Single-chip Transceiver Tdm/utopia Ii Interface
• Manufacturer: Maxim Integrated Products, Inc.

The example in Figure 24-3 shows where the transmission of cells though the transmit interface is
stopped by the ATM, as no PHY is ready to accept cells. Polling continues. Several clock cycles later one
PHY gets ready to accept a cell. During the transmission pause, the UT-DATAx and UT-SOC can go into
high-impedance state as shown. UT-ENB is held in deasserted state. When a PHY is found that is ready to
accept a cell (PHY_N + 3 in this case), the address of this PHY must be applied again to select it. This is
necessary because of the 2-clock polling cycle, where the PHY is detected at the clock edge #15. At this
time, the address of PHY N + 3 is no longer on the bus and therefore must be applied again in the next
clock cycle. PHY N + 3 is selected with clock edge #16.
Figure 24-3. End and Restart of Cell at Transmit Interface
CELL XMIT TO:
UT-ADDRx
UT-DATAx
UT-CLAV
UT-ENB
UT-CLK
UT-SOC
1
N+1
P45
2
N+1
P46
PHY N
1F
3
P47
N
4
P48
N
1F
5
N+3
6
N+3
1F
POLLING
7
N+2
8
N+2
1F
173 of 265
9
N-1
10
N-1
1F
11
N
12
DETECTION
N
1F
13
N+3
14
SELECTION
N+3
1F
15
N+3
16
N+3
1F
H1
17
N-2
H2
18
PHY N+3
POLLING
N-2
1F
H3
19
N-3
H4
20